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MPC-WORKSHOP FEBRUAR 2013
Figure 4: Readout circuit diagram. The chain is consists of an
integrator, track-and-hold stage and an ADC.
B. Readout
The readout chain consists of an integrator, a trackand-hold
stage, and an ADC. Figure 4 shows the
readout diagram.
The stability of voltage at the output node of the
sensor core significantly affects the linearity performance.
Hence, an active stage with feedback is preferred
to keep this voltage constant during operation.
The integrator topology has a number of advantages
for this task. First, it serves as a low-pass filter and
suppresses noise. Second, the voltage of the input
node is kept constant due to feedback. Finally and
most importantly, the feedback loop only accommodates
a capacitor which is stress insensitive. The feedback
behavior remains the same under varying stress
unlike resistive feedback structures.
A two stage miller op-amp is used for the integrator.
The amplifier is designed to remain within acceptable
limits under stress values up to 200 MPa. This may
cause a mobility change up to ±15 %, depending on
the direction of the stress vector. The fundamental
practice is to place all transistors of the same type in
the same direction. Therefore, the parameter changes
in the differential branches are cancelled out and it is
easier to take account of a global mobility change for
all transistors of the same type. Further measures are
taken for higher stress insensitivity, as gain and phase
margin are explicitly affected. The phase margin is
pushed above 60° at the cost of higher power consumption.
The minimum gain is set to be 80 dB for
minimizing the voltage drift at the input node under
stress.
The track-and-hold circuit is intrinsically not affected
by stress. The size of the capacitor is selected considering
the load of the integrator and the kickback of
the ADC. Complementary switches with charge injection
cancellation are used.
A 10-bit successive approximation register ADC
from the IMS CHIPS intellectual property library is
used for digitization. The ADC has a rail-to-rail input
range and requires 20 clock cycles for one complete
conversion. The stress insensitivity of the device is
established by careful layout and design measures.
Figure 5: Digital controller block diagram. Conceptual diagram is
deduced from VHDL code and simplified for clarity.
C. Digital Controller
The management of the analog blocks and external
communication is to be done by the designed controller.
It is written in VHDL and realized using silicon
compiling tools. Figure 5 shows the controller block
diagram.
The readout timing determines the post-readout calculation
and affects the overall performance. The
controller supports external programming which enables
testing different cases on silicon. The timing can
be adjusted as precise as one pulse of system clock.
Fine tuning of pulse widths and sequence of activities
enable optimization of important system performance
figures such as sensor bandwidth, noise performance,
and dynamic range.
The number of pads is minimized by serializing the
sensor I/O’s. The data exchange with external electronics
is done via two serial synchronous interfaces
that are used for sensor configuration and ADC data
read-out.
IV. IMPLEMENTATION
Several intrinsic and extrinsic restrictions are present
in layout level due to the gate array technology and
stress exposure. All circuits except stress sensor cores
are constructed with same-oriented transistors due to
gate array technology. Differential branches in the
analog and digital circuitry benefit from uniform
alignment as stress effects are nulled out. The stress
sensor cores are built using the special [110], [1¯10],
[100], and [010] oriented transistors in the used gate
array master. Figure 6 illustrates the orthogonal transistor
pairs in the master used for this work.
Analog and digital circuits are implemented in their
indigenous regions resulting from the technology. The
wells and supplies of analog and digital domains are
separated in order to minimize crosstalk. Chip size is
4.5 mm x 4.5 mm.
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