Workshopband als PDF - Mpc.belwue.de

MPC-WORKSHOP FEBRUAR 2013
Figure 5: Set-up for Implementation
The dv signal helps the SYN detection block to read
the incoming bits. Due to the start-up delay in the
DPLL the SYN Detection block only takes into account
the last 6 bits of the SYN pattern, that is, if the
string “010100” is detected, a SYNC pattern will be
considered positive. The SYN detection block also
searches for long strings of ones to detect an idle state.
3) NRZI Decoding and De-Bit Stuffing Block
The NRZI decoding block must read a bit when the
dv signal is high to guarantee the correct value has
been stored. Much in the same way, it must deliver a
new data valid signal to compensate the delay along
with the decoded data. The de-bit stuffing block is
designed as a finite state machine with the purpose to
extract the 0 bit whenever 6 consecutive ones are
found. This task is done only by not activating the data
valid signal output whenever the zero should be extracted.
4) CRC Verification Block
The CRC verification block is activated after the
PID field has been read and it is disabled when the
EOP is detected. There are 2 internal verification
blocks, one to check the CRC-5 and the second for
CRC-16, and they both work with the exact logic as
the CRC calculators. They calculate the CRC from the
data being received and compares it to the residual,
mentioned in table 2, to check if there were any errors
in the process.
5) Shift Register and Registers for Saved Data
The shift register is a simple 16 bit register to load
the incoming data before transferring it to the registers
for saved data. It takes the data coming from the de-
bit stuffing block when the valid signal is high and
saves it. The 16 bits of the shift register are loaded
into a word of the registers for saved data structure
when the control state machine gives the write signal
in the address provided.
If the microcontroller wishes to read the information
stored, it uses the input sel of the receiving block; the
four msb chooses the word that will appear in the
parallel output Q; the four lsb runs each of the
bits into the serial output Q. After the receiving
process is over, the control state machine writes the
number of words received into the last register, that
way when the data wants to be read out, the first step
is to read address 1111B for the number of bytes to be
read out.
6) Control State Machine for Reception
The Control State Machine takes care of every control
line in whole receiving structure. The Receptor
Structure offers the possibility to start saving in a
specific register, this is indicated by the adr and mode
inputs. If mode is one the control state machine loads
the address from adr to start saving, otherwise it will
start in address zero. If run is activated and either an
EOP or a line of ones (idle state) is detected the waiting
to detect a valid SYN pattern begins. Once this
happens the enable signal for the de- bit stuffing is
activated and the process of reception starts.
When the EOP is detected, the control state machine
saves the last data into a register along with the number
of words received and the CRC Verification is
checked. If the data received was only the PID plus 16
bits the CRC5 is taken into account, if there were
more bytes received then the CRC16 is checked.
The outputs of the block are flags; if there is new
data stored the dv_st flag is set, if the correct CRC
was a match the CRC_ok flag is set. The ovrun flag is
set when the last possible register is written to and
there is no more place to save data. The flags are
maintained until the run signal is turned off; once the
run signal is off the flags are reset and the CRCs
cleared.
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