Workshopband als PDF - Mpc.belwue.de

Table 5: Data Registers
Address Register
0x10 SYN
it after the ENDP field. At the end of the transmission
it provides the EOP for the needed 2 bit times.
3) Data Packets Structure
The block for data packets has the same logic behind
it as the block for token and handshake packets. It
begins with loading the data registers and ends with
the control state machine. The addresses for the block
of registers for the Data are stated in Table 5. The
NUM register tells how many bytes of data will be
transmitted.
The calculated CRC 16 is loaded directly from the
CRC 16 calculator. Whether the CRC calculated or
stored is used, is also stated by the CTRL register in
the Token and Handshake registers structure. All the
blocks in the Data structure are controlled by the control
state machine inside the data structure. Its performance
is almost the same as the one for token and
handshake packets; it keeps count of how many bytes
are sent, enables and clears the CRC16 calculator and
provides the time for the EOP.
4) Selection and Formatting of Output
This block is in charge of selecting between the token
and handshake packet serial output and the data
serial output to perform the bit stuffing, NRZI encoding
and the differential output. The selection is done
via some multiplexers controlled by the Drun and
THrun signals, during every transmission only one of
the two lines can be activated.
The bit stuffing sends a next signal to the control
state machines to ask for the next bit of the string,
when six one bits are encountered, the signal nxt is
stalled and a zero bit is inserted and endorsed with the
valid bit in the output section. After the bit stuffing is
done, the NRZI encoding and the differentiation of the
output take place.
54
0x11 PID
0x12
CRC stored
first byte
0x13
CRC stored
second byte
0x14-
0x33
Data Bytes
--
CRC 16
calculated
0xF0 NUM
C. Receiver
VHDL BASED CIRCUIT DESCRIPTION TO TRANSMIT,
RECEIVE AND ANALYSE USB DATA PACKETS
Figure 4: Receiver
The receiver is in itself divided into several different
structures: the differential input block, the blocks for
EOP and SYN detection, the block for synchronization,
the blocks for NRZI decoding, de-bit stuffing and
CRC checking, the block with the shift register and
the saved received data, and finally the control finite
state machine. The whole receiver structure is shown
in Figure 4.
1) EOP Detection and Differential Input Blocks
As inputs of the structure there are 2 D+ lines and 2
D-, one set of them go to the EOP detection block to
be able to recognise the SE0 part of the EOP. The
other set of lines are inputs of the differential input
block, where a primitive from the Xilinx Unified Libraries
for the Spartan 3E board was used, the
IBUFDS differential signaling input buffer with optional
delay, to retrieve the data from the differential
lines. Another function of the differential input block
is to do two samplings of the data line; first with the
positive edge of the clock, the second with the negative.
2) DPLL for Synchronization and SYN Detection
Blocks
A digital phase locked loop is implemented through
a state machine to keep track of the changes in the
data line in the positive and the negative edges of the
internal clock. Then some signals for data available dv
are created to indicate a reliable place of the bit cell to
be read, the best dv signal can be manually selected by
the input mux of the block. The DPL needs at least 2
changes in the lines to lock the internal clock with the
signal.