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2.0 Mb DTI/PRI Administration and Maintenance Guide Book ... - Home

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Page 944 of 1536 Chapter 7 — <strong>DTI</strong> <strong>Maintenance</strong><br />

Clock Controller comm<strong>and</strong>s<br />

2 <strong>Mb</strong> <strong>DTI</strong> tests<br />

Below is a quick reference list of clock controller comm<strong>and</strong>s in LD 60.<br />

Comm<strong>and</strong> Action<br />

DIS CC 0 disable clock controller N<br />

ENL CC 0 enable clock controller N<br />

SSCK 0 status of clock controller N<br />

TRCK XXX set clock controller tracking. XXX can be:<br />

PCK track primary clock reference source<br />

SCLK track secondary clock reference source<br />

FRUN free run mode<br />

Self test/Local loopback<br />

The NTAK10 self-tests when requested in LD 60. This procedure checks the<br />

sanity of the on board processors, operation of memory <strong>and</strong> peripheral<br />

hardware as well as per-channel <strong>and</strong> per-loop loopback.<br />

Before this test is run, the loop must be disabled as follows:<br />

1 Disable the NTAK10 using LD 60:<br />

LD 60<br />

DISL L CH<br />

2 Run the self-test using LD 60:<br />

LD 60<br />

SLFT L (for the entire loop)<br />

SLFT L CH (for a specific channel<br />

553-3011-315 St<strong>and</strong>ard 10.0 May 1999

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