High Performance Microchip Supply - Under Secretary of Defense ...

FINDINGS ___________________________________________________________________
stockpile stewardship, engineering, and process development
requirements. These facilities historically provided classified or
highly sensitive products, but did not address the need for “trusted”
supplies for a larger set of DOD weapon system devices; there were
sufficient U.S. firms willing and able to satisfy the then–state-of-theart
needs.
There is no longer a diverse base of U.S. IC fabricators capable of
meeting trusted and classified chip needs.
DOD has initiated a trusted foundry program to provide, in the
interim, a source of high-performance ICs in accordance with the
overall defense trusted integrated circuit supply (DTICS) mandate.
DOD has contracted for these services on a “take-or-pay” basis. 25
More information on the trusted foundry program can be found in
appendix F.
At this time, a single foundry contract has been let for leadingedge
fabrication (tier 1) 26 services with IBM. No foundry contracts
have been negotiated with tier 2 and 3 fabricators; however, the
larger number of fabricators available to produce ICs with processes
one or more generations behind the leading edge has resulted in
supplier competition to participate in the program. Sources of the
older tier 2 and tier 3 technologies are much more available; however,
a longer-term concern remains when the current tier 1 technology
becomes tier 2 and there are few U.S. facilities capable of practicing it.
The specific qualifications required of a foundry to be designated
“trusted” are the province of the trusted foundry program and
DTICS.
25. Presentation to the Defense Science Board Task Force on High-performance
Microelectronics by Chuck Varney, Chief, Trusted Access Program Office May 20, 2004.
26. For purposes of the Trusted Foundry Program, the term “Tier 1" refers to a foundry
having the state-of-the-art (leading edge) of commercial wafer fabrication technology.
At this time, the leading edge is a CMOS process with 90 nm minimum critical
dimensions. “Tier 2" is taken to refer to a foundry capable of processing wafer 2 to 4
generations behind the leading edge (now CMOS with 130, 180 or 250 nm critical
dimensions), “Tier 3" refers to foundries with wafer processing capabilities even further
behind.
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