High Performance Microchip Supply - Under Secretary of Defense ...

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RECOMMENDATIONS ____________________________________________________________ − Establish current best practices for detecting and preventing subversive techniques, keeping in mind cost, both in money and time. 42 An investment strategy for enhancing U.S. countertamper evaluation capabilities should be developed. Current and projected capabilities must be highly protected; insight into U.S. detection abilities allows an adversary to tailor offensive approaches to reduce their cost and operational uncertainty. Establish an aggressive national antitamper development and evaluation program. Once the appropriate level of trust is established for a given component, effective, manufacturable, and affordable antitamper technology must be applied to the component to ensure the maintenance of trust. Initiate an annual competition to exercise the defensive approaches outlined above. This competition will provide estimates of the effectiveness of defensive techniques and increase confidence in the risk management process. Assess the subversion vulnerabilities of FPGAs. The innovative application of FPGAs in DOD critical systems shows great promise. However, aggressive adversarial analysis of these approaches has not been initiated. A strategy for achieving the above hardware countertamper objectives without a comparable strategy for software is of limited utility. The task force recommends DDR&E Commission a similar DSB study to investigate national security issues associated with rapid 42. These items are recommended tasks for the IC. 78 _________________________________________________________ DSB TASK FORCE ON
___________________________________________________________ RECOMMENDATIONS migration of software production, testing, and maintenance overseas. Develop a national security strategy with corresponding implementation plan that couples the recommendations of the microelectronic and software studies and ensures that they are in balance and mutually supportive. HIGH PERFORMANCE MICROCHIP SUPPLY ___________________________________________ 79
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Defense Science Board Task Force On
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TABLE OF CONTENTS__________________
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EXECUTIVE SUMMARY _________________
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INTRODUCTION ______________________
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INTRODUCTION ______________________
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INTRODUCTION ______________________
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INTRODUCTION ______________________
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INTRODUCTION ______________________
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INTRODUCTION ______________________
Page 34 and 35: FINDINGS __________________________
Page 62 and 63: RECOMMENDATIONS ___________________
Page 88: TERMS OF REFERENCE ________________
Page 92 and 93: TERMS OF REFERENCE ________________
Page 94: DEPUTY SECRETARY OF DEFENSE MEMO __
Page 98 and 99: FUTURE TECHNOLOGY DEVELOPMENT _____
Page 104 and 105: RANDY GOODALL SEMATECH ____________
Page 106 and 107: TRUSTED FOUNDRY PROGRAM ___________
Page 108 and 109: TRUSTED FOUNDRY PROGRAM ___________
Page 110 and 111: COMPARISON OF ASIC AND FPGA SYSTEM
Page 112 and 113: DFAR SUPPLEMENT ___________________
Page 114 and 115: MINORITY REPORT ___________________
Page 116 and 117: ACRONYMS __________________________
Page 118: ___________________________________
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High Performance Microchip Supply - Under Secretary of Defense ...

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