Statement List (STL) - DCE FEL ČVUT v Praze

Shift and Rotate Instructions
11.1.3 SSD Shift Sign Double Integer (32-Bit)
Formate
Description
Status word
SSD
SSD
Address Data type Description
integer, unsigned number of bit positions to be shifted, range
from 0 to 32
SSD (shift right with sign double integer) shifts the entire contents of ACCU 1 to the
right bit by bit. The bit places that are vacated by the shift instruction are filled with
the signal state of the sign bit. The bit that is shifted out last is loaded into the status
word bit CC 1. The number of bit positions to be shifted is specified either by the
address or by a value in ACCU 2-L-L.
SSD : The number of shifts is specified by the address . The
permissible value range is from 0 to 32.The CC 0 and OV status word bits are reset
to 0 if is greater than 0. If is equal to 0, the shift instruction is
regarded as a NOP operation.
SSD: The number of shifts is specified by the value in ACCU 2- L- L. The possible
value range is from 0 to 255. A shift number > 32 always produces the same result
(ACCU 1 = 32#00000000, CC 1 = 0 or ACCU 1 = 32#FFFFFFFF, CC 1 = 1). If the
shift number is greater than 0, the status word bits CC 0 and OV are reset to 0. If the
shift number is zero, then the shift instruction is regarded as an NOP operation.
BR CC 1 CC 0 OV OS OR STA RLO /FC
writes: - x x x - - - - -
Statement List (STL) for S7-300 and S7-400 Programming
11-4 A5E00706960-01