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Statement List (STL) - DCE FEL ČVUT v Praze

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1.17 R Reset<br />

Format<br />

R <br />

Address Data type Memory area<br />

BOOL I, Q, M, L, D<br />

Bit Logic Instructions<br />

Description<br />

R (reset bit) places a "0" in the addressed bit if RLO = 1 and master control relay<br />

MCR = 1. If MCR = 0, then the addressed bit will not be changed.<br />

Status word<br />

Example<br />

BR CC 1 CC 0 OV OS OR STA RLO /FC<br />

writes: - - - - - 0 x - 0<br />

<strong>STL</strong> Program<br />

A I 1.0<br />

S Q 4.0<br />

A I 1.1<br />

R Q 4.0<br />

Signal state diagrams<br />

I 1.0<br />

I 1.1<br />

Q 4.0<br />

1<br />

0<br />

1<br />

0<br />

1<br />

0<br />

Power rail<br />

I 1.0<br />

NO contact<br />

NC Contact<br />

Q 4.0<br />

Coils<br />

Relay Logic<br />

Q 4.0<br />

<strong>Statement</strong> <strong>List</strong> (<strong>STL</strong>) for S7-300 and S7-400 Programming<br />

A5E00706960-01 1-17<br />

I 1.1

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