Statement List (STL) - DCE FEL ČVUT v Praze

Shift and Rotate Instructions
11.1.7 SRD Shift Right Double Word (32-Bit)
Formate
Description
Status word
SRD
SRD
Address Data type Description
integer, unsigned number of bit positions to be shifted, range
from 0 to 32
SRD (shift right double word) shifts the entire contents of ACCU 1 to the right bit by
bit. The bit places that are vacated by the shift instruction are filled with zeros. The bit
that is shifted out last is loaded into the status word bit CC 1. The number of bit
positions to be shifted is specified either by the address or by a value in
ACCU 2-L-L.
SRD : The number of shifts is specified by the address . The
permissible value range is from 0 to 32. The status word bits CC 0 and OV are reset
to 0 if is greater thnan zero. If is equal to 0, the shift instruction
is regarded as a NOP operation.
SRD: The number of shifts is specified by the value in ACCU 2- L- L. The possible
value range is from 0 to 255. A shift number >32 always produces the same result:
ACCU 1 = 0, CC 1 = 0, CC 0 = 0, and OV = 0. If 0 < shift number