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Statement List (STL) - DCE FEL ČVUT v Praze

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1.23 FN Edge Negative<br />

Format<br />

FN <br />

Bit Logic Instructions<br />

Address Data type Memory area Description<br />

BOOL I, Q, M, L, D Edge flag, stores the previous<br />

signal state of RLO.<br />

Description<br />

FN (Negative RLO edge) detects a falling edge when the RLO transitions from<br />

"1" to "0", and indicates this by RLO = 1.<br />

During each program scan cycle, the signal state of the RLO bit is compared with<br />

that obtained in the previous cycle to see if there has been a state change. The<br />

previous RLO state must be stored in the edge flag address () to make the<br />

comparison. If there is a difference between current and previous RLO "1" state<br />

(detection of falling edge), the RLO bit will be "1" after this instruction.<br />

Status word<br />

Definition<br />

Note<br />

The instruction has no point if the bit you want to monitor is in the process image<br />

because the local data for a block are only valid during the block's runtime.<br />

BR CC 1 CC 0 OV OS OR STA RLO /FC<br />

writes: - - - - - 0 x x 1<br />

RLO<br />

1<br />

0<br />

Positive Edge Negative Edge<br />

Time<br />

<strong>Statement</strong> <strong>List</strong> (<strong>STL</strong>) for S7-300 and S7-400 Programming<br />

A5E00706960-01 1-23

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