Statement List (STL) - DCE FEL ČVUT v Praze

1.24 FP Edge Positive
Format
FP
Bit Logic Instructions
Address Data type Memory area Description
BOOL I, Q, M, L, D Edge flag, stores the previous
signal state of RLO.
Description
FP (Positive RLO edge) detects a rising edge when the RLO transitions from
"0" to "1" and indicates this by RLO = 1.
During each program scan cycle, the signal state of the RLO bit is compared with
that obtained in the previous cycle to see if there has been a state change. The
previous RLO state must be stored in the edge flag address () to make the
comparison. If there is a difference between current and previous RLO "0" state
(detection of rising edge), the RLO bit will be "1" after this instruction.
Status word
Definition
Note
The instruction has no point if the bit you want to monitor is in the process image
because the local data for a block are only valid during the block's runtime.
BR CC 1 CC 0 OV OS OR STA RLO /FC
writes: - - - - - 0 x x 1
RLO
1
0
Positive Edge Negative Edge
Time
Statement List (STL) for S7-300 and S7-400 Programming
A5E00706960-01 1-25