Statement List (STL) - DCE FEL ČVUT v Praze

Conversion Instructions
3.11 NEGD Twos Complement Double Integer (32-Bit)
Format
Description
Status word
Example
NEGD
NEGD (twos complement double integer) forms the twos complement of the 32-bit
value in ACCU 1. Forming the twos complement inverts the value bit by bit, that is,
zeros replace ones and ones replace zeros; then a "1" is added. The result is stored
in accumulator 1. The twos complement instruction is equivalent to a multiplication
by "-1" The instruction is executed without regard to, and without affecting, the RLO.
The status bits CC 1, CC 0, OS, and OV are set as a function of the result of the
operation.
BR CC 1 CC 0 OV OS OR STA RLO /FC
writes: - x x x x - - - -
Status word generation CC 1 CC 0 OV OS
Result = 0 0 0 0 -
-2.147.483.648 = 1 1 0 0 -
Result = 2 147 483 648 0 1 1 1
STL Explanation
L ID8 //Load value into ACCU 1.
NEGD //Generate twos complement (32-bit).
T MD10 //Transfer result to MD10.
Contents ACCU1-H ACCU1-L
Bit 31 . . . . . . . . . . 16 15 . . . . . . . . . . 0
before execution of
NEGD
0101 1111 0110 0100 0101 1101 0011 1000
after execution of NEGD 1010 0000 1001 1011 1010 0010 1100 1000
Statement List (STL) for S7-300 and S7-400 Programming
A5E00706960-01 3-11