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Statement List (STL) - DCE FEL ČVUT v Praze

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Counter Instructions<br />

4.8 CD Counter Down<br />

Format<br />

CD <br />

Address Data type Memory area Description<br />

COUNTER C Counter, range<br />

depends on CPU.<br />

Description<br />

CD decrements the count of the addressed counter by 1 when RLO<br />

transitions from "0" to "1" and the count is greater than 0. When the count reaches its<br />

lower limit of "0", decrementing stops. Additional transitions of RLO have no effect as<br />

the counter will not count with negative values.<br />

Status word<br />

Example<br />

BR CC 1 CC 0 OV OS OR STA RLO /FC<br />

writes: - - - - - 0 - - 0<br />

<strong>STL</strong> Explanation<br />

L C#14 //Counter preset value.<br />

A I 0.1 //Preset counter after detection of rising edge of I 0.1.<br />

S C1 //Load counter 1 preset if enabled.<br />

A I 0.0 //One count down per rising edge of I 0.0.<br />

CD C1 //Decrement counter C1 by 1 when RL0 transitions from 0 to 1 depending on input<br />

I 0.0.<br />

AN C1 //Zero detection using the C1 bit.<br />

= Q 0.0 //Q 0.0 = 1 if counter 1 value is zero.<br />

<strong>Statement</strong> <strong>List</strong> (<strong>STL</strong>) for S7-300 and S7-400 Programming<br />

4-8 A5E00706960-01

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