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Statement List (STL) - DCE FEL ČVUT v Praze

Statement List (STL) - DCE FEL ČVUT v Praze

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Word Logic Instructions<br />

13.3 OW OR Word (16-Bit)<br />

Format<br />

OW<br />

OW <br />

Address Data type Description<br />

WORD,<br />

16-bit constant<br />

Description of instruction<br />

Status word<br />

Bit pattern to be combined with ACCU 1-L by<br />

OR<br />

OW (OR word) combines the contents of ACCU 1-L with ACCU 2-L or a 16<br />

bit-constant bit by bit according to the Boolean logic operation OR. A bit in the result<br />

word is "1" when at least one of the corresponding bits of both words combined in the<br />

logic operation is "1". The result is stored in ACCU 1-L. ACCU 1-H and ACCU 2 (and<br />

ACCU 3 and ACCU 4 for CPUs with four ACCUs) remain unchanged. The instruction<br />

is executed without regard to, and without affecting, the RLO. The status bit CC 1 is<br />

set as a result of the operation (CC 1 = 1 if result is unequal to zero). The status word<br />

bits CC 0 and OV are reset to 0.<br />

OW: Combines ACCU 1-L with ACCU 2-L.<br />

OW : Combines ACCU 1-L with a 16-bit constant.<br />

BR CC 1 CC 0 OV OS OR STA RLO /FC<br />

writes: - x 0 0 - - - - -<br />

<strong>Statement</strong> <strong>List</strong> (<strong>STL</strong>) for S7-300 and S7-400 Programming<br />

13-4 A5E00706960-01

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