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Statement List (STL) - DCE FEL ČVUT v Praze

Statement List (STL) - DCE FEL ČVUT v Praze

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Bit Logic Instructions<br />

1.20 SET Set RLO (=1)<br />

Format<br />

Description<br />

Status word<br />

Example<br />

SET<br />

SET sets the RLO to signal state "1".<br />

BR CC 1 CC 0 OV OS OR STA RLO /FC<br />

writes: - - - - - 0 1 1 0<br />

<strong>STL</strong> Program Signal State Result of Logic Operation (RLO)<br />

SET<br />

1<br />

= M 10.0<br />

= M 15.1<br />

= M 16.0<br />

CLR<br />

= M 10.1<br />

= M 10.2<br />

1<br />

1<br />

1<br />

0<br />

0<br />

<strong>Statement</strong> <strong>List</strong> (<strong>STL</strong>) for S7-300 and S7-400 Programming<br />

1-20 A5E00706960-01<br />

0

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