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Statement List (STL) - DCE FEL ČVUT v Praze

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Counter Instructions<br />

4.2 FR Enable Counter (Free)<br />

Format<br />

Description<br />

Status word<br />

Example<br />

FR <br />

Address Data type Memory area Description<br />

COUNTER C Counter, range<br />

depends on CPU.<br />

When RLO transitions from "0" to "1", FR clears the edge-detecting flag<br />

that is used for setting and selecting upwards or downwards count of the addressed<br />

counter. Enable counter is not required to set a counter or for normal counting This<br />

means that in spite of a constant RLO of 1 for the Set Counter Preset Value, Counter<br />

Up, or Counter Down, these instructions are not executed again after the enable.<br />

BR CC 1 CC 0 OV OS OR STA RLO /FC<br />

writes: - - - - - 0 - - 0<br />

<strong>STL</strong> Explanation<br />

A I 2.0 //Check signal state at input I 2.0.<br />

FR C3 //Enable counter C3 when RLO transitions from 0 to 1.<br />

<strong>Statement</strong> <strong>List</strong> (<strong>STL</strong>) for S7-300 and S7-400 Programming<br />

4-2 A5E00706960-01

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