BSP Developer's Guide

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Driver Guidelines
5.8 Driver Use of the Cache Library
Before reading this section, review the reference entry for cacheLib. This section
describes how to maintain data cache coherency for device drivers by using the
VxWorks cache library (cacheLib). It also describes the cacheLib mechanism for
controlling the side effects of CPU write piping, and provides additional hints for
handling cache-related issues in your device driver.
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5.8.1 Review of cacheLib Facilities
The cacheLib reference entries describe the library’s facilities in detail. This section
provides a brief definition of the facilities discussed in this document. Remember
that the cacheLib.h header file contains the function prototypes and macros need
to make use of the cacheLib facilities. Include this file in your driver code.
This document also references the following routine and macros:
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The cacheDmaMalloc( ) routine allocates memory from the system. It
attempts to use the underlying hardware features to provide a memory region
that is safe from cache coherency issues. This memory region is guaranteed to
start on a cache line boundary, and not to overlap cache lines with adjacent
regions.
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The CACHE_DMA_xxxx macros (such as CACHE_DMA_FLUSH) flush,
invalidate, and learn attributes of memory regions provided by the
cacheDmaMalloc( ) routine.
The CACHE_DRV_xxxx macros (such as CACHE_DRV_INVALIDATE) flush,
invalidate, and learn attributes of ordinary memory that the driver controls.
The CACHE_USER_xxxx macros (such as
CACHE_USER_IS_WRITE_COHERENT) flush and invalidate user memory that
is outside the domain of the driver.
5.8.2 Conducting Driver Analysis
Each driver has a set of attributes that define its behavior relative to the cache. This
section provides some guidelines for analyzing your driver for potential cache
coherency problems. When you know the driver’s attributes, you can create a
strategy for use of the cacheLib routines in the driver.
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