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BSP Developer's Guide

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VxWorks 5.5<br />

<strong>BSP</strong> Developer’s <strong>Guide</strong><br />

It is recommended that you use CACHE_PIPE_FLUSH between an I/O write<br />

operation and a following I/O read operation. Successive writes or reads should<br />

not require any special protection. It is only when switching from writing to<br />

reading that pipeline flushing becomes essential.<br />

Note that flushing of the write pipeline does not mean the cache is automatically<br />

flushed to memory as well. You must still handle cache issues within the driver.<br />

Conversely, flushing or disabling the cache does not automatically flush or disable<br />

the write pipeline. The write pipeline is first in the hierarchy.<br />

SNOOPED Attribute<br />

This attribute is transparent to all memory types. Portable drivers use the<br />

appropriate flush and invalidate macros. However, if SNOOPED is TRUE, the<br />

macros evaluate to null operations. Target-specific drivers do not need flush or<br />

invalidate macros.<br />

Some systems implement partial snooping. They can read snoop and only<br />

invalidate cache data on a write. This does not meet the requirements for fully<br />

coherent memory. In this case, the SNOOPED attribute is FALSE not TRUE.<br />

MMU_TAGGING Attribute<br />

This attribute is transparent to the memory type obtained using the<br />

cacheDmaMalloc( ) routine. Portable drivers use the CACHE_DMA_FLUSH and<br />

CACHE_DMA_INVALIDATE macros. However, if MMU_TAGGING is TRUE, the<br />

macros evaluate to null operations. Target-specific drivers do not need<br />

CACHE_DMA_FLUSH or CACHE_DMA_INVALIDATE macros.<br />

This attribute does not typically affect memory obtained using the malloc( )<br />

routine, the data section, or the bss section. Therefore, appropriate use of the<br />

CACHE_USER_xxxx and CACHE_DRV_xxxx flush and invalidate macros is<br />

required, as described in Flush and Invalidate Macros, p.107.<br />

USER_DATA_UNKNOWN Attribute<br />

With this attribute, your driver must maintain cache coherency of any data that is<br />

passed directly between the device and the user. For outgoing data, first flush the<br />

user data from the cache with the CACHE_USER_FLUSH macro before<br />

commanding the device to access the data. For incoming data, first invalidate the<br />

108

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