BSP Developer's Guide

5
Driver Guidelines
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Memory that is of unknown origin. This memory is associated with the
CACHE_USER_xxxx macros and is outside the control of the driver. In other
words, the driver does not really know how the memory was allocated, but the
CACHE_USER_xxxx macros assume the memory was allocated using malloc( ).
Memory that is of a fixed or special purpose. This memory is a special region
that is provided by the target hardware and is intended for the exclusive use
of a DMA-type device. This is usually done for performance reasons. This
memory is not part of the system pool, and thus is not associated with the
malloc( ) routine, the cacheDmaMalloc( ) routine, the data section, or the bss
section. There are no cache macros associated with this type of memory. The
hardware usually provides a means to make this entire region non-cacheable.
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Driver Attributes
This section lists the driver attributes you need to be aware of when planning your
cacheLib strategy. Each attribute is given a name to simplify later discussion.
Other than write pipelining, the attributes are of concern only to a DMA-type of
device.
WRITE_PIPING
The CPU uses write pipelining. Write pipelining means that write operations of
the CPU are held in a pipeline until the optimum state of the external bus
occurs. Write pipelining is used on RISC architectures, such as MIPS. This
technique can seriously affect your driver because it can delay the delivery of
commands or data to the device your driver controls.
This attribute is TRUE if the driver is to be run on a CPU that has a write pipe.
USER_DATA_UNKNOWN
The user data is in an unknown state. This attribute is TRUE if your driver
passes data by address directly between the device and the driver’s user. In
this case, data handed to the driver by the user is of an unknown cache state.
An example of this is a pointer to a data buffer given to a SCSI disk driver for
writing to the disk. In this case, the driver does not know if the buffer has been
flushed to memory, or is still in cache. Conversely, data that is obtained from
the device must be coherent between cache and memory before the pointer to
that data can be given to the user for consumption.
MMU_TAGGING
The hardware provides MMU tagging of cache regions.This attribute is TRUE
if an MMU that allows tagging of memory regions as non-cacheable is
available on the target hardware.
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