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BSP Developer's Guide

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Contents<br />

3.6.5 Cache, MMU, and DMA Devices .................................................... 60<br />

3.6.6 Boot ROMs .......................................................................................... 60<br />

3.6.7 SCSI ...................................................................................................... 61<br />

3.6.8 Projects ................................................................................................. 61<br />

4 Hardware <strong>Guide</strong>lines ................................................................................................ 63<br />

4.1 Introduction ...................................................................................................... 63<br />

4.2 Architectural Considerations .......................................................................... 64<br />

4.2.1 Interrupt Handling ............................................................................ 64<br />

4.2.2 Cache Issues ........................................................................................ 65<br />

4.2.3 MMU Support .................................................................................... 66<br />

4.2.4 Floating-Point Support ...................................................................... 66<br />

4.2.5 Other Issues ........................................................................................ 67<br />

4.3 Memory .............................................................................................................. 67<br />

4.3.1 RAM ..................................................................................................... 68<br />

4.3.2 ROM ..................................................................................................... 68<br />

4.3.3 Ethernet RAM ..................................................................................... 68<br />

4.3.4 NVRAM ............................................................................................... 69<br />

4.3.5 Parity Checking .................................................................................. 69<br />

4.3.6 Addressing .......................................................................................... 69<br />

4.3.7 Bus ........................................................................................................ 70<br />

VMEbus ............................................................................................... 70<br />

Multibus II ........................................................................................... 74<br />

PCI, cPCI, and PMC ........................................................................... 76<br />

Busless ................................................................................................. 76<br />

4.4 Devices ............................................................................................................... 76<br />

4.4.1 Interrupts ............................................................................................. 77<br />

4.4.2 System Clock ...................................................................................... 79<br />

vii

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