BSP Developer's Guide

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VxWorks 5.5 BSP Developer’s Guide If this test is run between two targets using shared memory, make sure the target is configured to include shared memory show routines. To do this, add INCLUDE_SHOW_ROUTINES to config.h of the BSPs or include the component INCLUDE_SM_NET_SHOW, if using project facility. NOTE: This reference entry lists the most likely reasons for a test’s failure. However, it does not list all possible reasons. The script does not reboot the targets. It assumes that the two targets and their respective target servers are up and running. By default the test assumes that T1 target is the system controller on the common VME backplane. An optional configuration parameter T1_BUS_MASTER can be set to FALSE to override this default configuration. In this case the T2 target is assumed to be the system controller. It is necessary to make sure that T1_BUS_MASTER has the correct value in case targets have to be rebooted before running any test. The test starts by obtaining two cache-coherent memory locations by calls to cacheDmaMalloc( ) on the master. These two memory locations are used for the semaphore and the access counter. The pkTestRamByte function checks that the addresses returned by cacheDmaMalloc( ) are readable and writable. Next, the local addresses are used to compute the bus addresses by calling the function sysLocalToBusAdrs( ) on the master. The bus addresses returned by sysLocalToBusAdrs( ) are passed to the slave, which uses the function sysBusToLocalAdrs( ) to get its own local addresses that it must apply to access the semaphore and counter locations on the master’s shared memory. The smAdrsFind procedure is called to verify that the counter and semaphore locations are seen by both the master and the slave. The memory locations are then initialized and the test is started by spawning the pkTasTest task on both master and slave. The functions wtxContextCreate( ) and wtxContextResume( ) are used here to spawn and start the tasks. The function pkTasTest( ) uses the semaphore location for mutual exclusion. When the master gets the semaphore, it increments the counter, if it is odd, and runs a busy-wait loop until it finally clears the semaphore. The slave runs the same way except that it increments the counter if it is even. This scheme ensures that the two tasks take turns grabbing the semaphore and incrementing the counter. The counter is monitored from the script, which takes two readings of the counter one second apart. If the second reading is larger than the first one, the short-term test is successful. After a pause of ten minutes, the two readings are retaken. If the counter is still increasing, the long-term test is successful. If this test fails, check that the master and slave are both accessing the same two master memory locations. If the master sysLocalToBusAdrs( ) or the slave sysBusToLocalAdrs( ) routines are not functioning properly, the test will not be able to find appropriate slave addresses that access the master memory locations. The master memory locations must be cache-coherent and must be writable. The VME controller chips must be initialized to 378
J BSP Validation Test Suite Reference Entries CONFIGURATION PARAMETERS proper values. For fast target boards, it might be necessary to increase the busy-wait delays given by the T1_TAS_DELAY (T2_TAS_DELAY) macro. The two tests in this script require two unique cache-coherent memory locations on master that can be accessed by both master and slave. By default, these locations are obtained by calls to cacheDmaMalloc( ) on the master. Alternatively, the macros T1_COUNT_ADRS and/or T1_SEM_ADRS can be changed from the default of “-1” to point to unique shared memory addresses on master. In this case, the user must make sure that these are free cache-coherent memory locations. The ability to explicitly declare these locations is provided for debugging purposes and for boards with hardware limitations. The final validation should leave the macros set to “-1”, and allocate the memory dynamically by calling cacheDmaMalloc( ). Barring serious hardware or software limitations (such as an identifiable VxWorks problem), the target board must pass all tests for the BSP to be validated. Of course, if the VME backplane is not supported by the target board, then this test is not a BSP validation requirement. T1_COUNT_ADRS Address of master’s shared counter (optional). T1_SEM_ADRS Address of master’s shared semaphore (optional). T1_TAS_DELAY Busy delay during TAS on master (optional). T2_TAS_DELAY Busy delay during TAS on slave (optional). EXAMPLE SEE ALSO Output consists of: BSP VALIDATION TEST ------------------- Target server : t53-160 BSP : mv147 Second target server : t214-2 Second BSP : mv147 Log file : /tmp/bspValidationLog.6425 busTas: short-term TAS test : PASS long-term TAS test : PASS Tests RUN 2 Tests PASSED 2 Tests FAILED 0 Tests SKIPPED 0 bspVal.sh, smLib.tcl, pkLib.c J 379
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VxWorks® 5.5 BSP DEVELOPER’S GUI
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1 Overview ........................
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Contents 1 Overview ...............
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Contents 3.6.5 Cache, MMU, and DMA
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Contents Memory-Mapped Chips ......
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Contents 7.3.3 System Configuration
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Contents 9.5.4 Processing .........
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Contents F Generic Drivers ........
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Contents Stopping the Driver Withou
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1 Overview 1.1 Introduction One str
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1 Overview ■ New Drivers Many new
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1 Overview Included with Tornado (n
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1 Overview ■ ■ ■ ■ ■ ■
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1 Overview Table 1-1 Font Usage for
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2 BSP Organization 2.1 Introduction
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2 BSP Organization Files in the tar
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2 BSP Organization Files in the tar
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2 BSP Organization Version 1.0 BSPs
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2 BSP Organization SM_MEM_SIZE The
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2 BSP Organization For boards witho
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2 BSP Organization PCI_MSTR_IO_LOCA
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2 BSP Organization The entry point
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2 BSP Organization target.nr The fi
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2 BSP Organization bootrom This fil
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2 BSP Organization sysSerialHwInit(
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2 BSP Organization The Motorola M68
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2 BSP Organization Many VxWorks fac
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2 BSP Organization further board in
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2 BSP Organization can have very un
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3 Creating a New BSP 3.1 Introducti
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3 Creating a New BSP 3.2 Setting Up
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3 Creating a New BSP Makefile At a
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3 Creating a New BSP char * sysBspR
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3 Creating a New BSP ... #endif } T
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3 Creating a New BSP int dummy; ...
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3 Creating a New BSP To find the so
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3 Creating a New BSP might want to
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3 Creating a New BSP not, use the s
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3 Creating a New BSP ■ It has a V
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3 Creating a New BSP 3.6.7 SCSI VxW
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4 Hardware Guidelines 4.1 Introduct
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4 Hardware Guidelines to the start
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4 Hardware Guidelines Higher-level
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4 Hardware Guidelines Such dedicate
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4 Hardware Guidelines Especially us
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4 Hardware Guidelines selected from
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4 Hardware Guidelines Hardware Inte
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4 Hardware Guidelines The rest of t
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4 Hardware Guidelines 4.4.2 System
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4 Hardware Guidelines only deal wit
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4 Hardware Guidelines 4.4.13 Parall
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4 Hardware Guidelines 0x10000, /* 6
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4 Hardware Guidelines The following
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5 Driver Guidelines 5.1 Introductio
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5 Driver Guidelines Maintenance and
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5 Driver Guidelines word addresses.
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5 Driver Guidelines 5.4 Design Guid
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5 Driver Guidelines Per-Device Data
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5 Driver Guidelines To fix this sit
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5 Driver Guidelines block are more
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5 Driver Guidelines 5.8 Driver Use
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5 Driver Guidelines ■ ■ Memory
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5 Driver Guidelines The level of ca
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5 Driver Guidelines cache for the d
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6 Components 6.1 Introduction Torna
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6 Components 6.2 Component Descript
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6 Components ■ User Presentation.
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6 Components Folder FOLDER_ANSI { N
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6 Components in a single project. I
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6 Components The component object i
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6 Components Parameters Parameters
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6 Components In the example, the co
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6 Components (2) comps/vxWorks/arch
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6 Components Figure 6-4 Include Com
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6 Components NOTE: INIT_BEFORE only
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6 Components The _CHILDREN property
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6 Components ! CAUTION: Do not alte
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6 Components ■ Check the Project
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7 Validation Testing 7.1 Introducti
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7 Validation Testing ■ ■ The te
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7 Validation Testing 2. The script
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7 Validation Testing Figure 7-4 Typ
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7 Validation Testing NOTE: Wind Riv
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7 Validation Testing scsi Requires
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7 Validation Testing Table 7-1 Vali
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7 Validation Testing Table 7-2 Vali
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7 Validation Testing sysProcNumGet
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7 Validation Testing The log file c
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8 Writing Portable C Code This chap
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8 Writing Portable C Code attribute
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8 Writing Portable C Code 8.1.3 Sta
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8 Writing Portable C Code 8.1.5 Oth
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8 Writing Portable C Code The last
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8 Writing Portable C Code Always sp
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8 Writing Portable C Code 8.2 Tool
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9 Documentation Guidelines 9.1 Intr
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9 Documentation Guidelines Spelling
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9 Documentation Guidelines Table 9-
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9 Documentation Guidelines Table 9-
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9 Documentation Guidelines ■ Avoi
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9 Documentation Guidelines ■ ■
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9 Documentation Guidelines INCLUDE
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9 Documentation Guidelines INTRODUC
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9 Documentation Guidelines 9.5 Gene
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9 Documentation Guidelines uppercas
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9 Documentation Guidelines The foll
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10 Product Packaging 10.1 SETUP Dev
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10 Product Packaging ... include $(
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10 Product Packaging Vendor-Supplie
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10 Product Packaging in the project
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A Upgrading a BSP for Tornado 2.0 T
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A Upgrading a BSP for Tornado 2.0 A
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A Upgrading a BSP for Tornado 2.0
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A Upgrading a BSP for Tornado 2.0 6
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B Upgrading a BSP for Tornado 2.2 T
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B Upgrading a BSP for Tornado 2.2 C
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B Upgrading a BSP for Tornado 2.2
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B Upgrading a BSP for Tornado 2.2 c
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B Upgrading a BSP for Tornado 2.2
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C Upgrading a BSP for the VxWorks N
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D VxWorks Boot Sequence Table D-1 d
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D VxWorks Boot Sequence Table D-1 V
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E Component Language E.1 Component
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E Component Language REQUIRES r1 r2
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E Component Language } // default i
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E Component Language FOLDER_WINDVIE
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E Component Language initialization
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E Component Language INCLUDE_MMU_BA
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E Component Language INCLUDE_NETWOR
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E Component Language INCLUDE_WDB_ME
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F Generic Drivers F.1 Introduction
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F Generic Drivers CONSOLE_TTY This
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F Generic Drivers Define SIO_CALLBA
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F Generic Drivers NV_RAM_SIZE Defin
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F Generic Drivers F.10 PCI Bus The
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G Upgrading 4.3 BSD Network Drivers
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H Implementing a MUX-Based Network
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I Writing a SCSI-2 Device Driver I.
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Index clocks see also individual cl
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Index naming conventions 95 perform
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Index INCLUDE_USR_APPL 38 INCLUDE_V
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Index network drivers 58 network in
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Index scsiCtrlLib 324 scsiDirectLib
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Index testing, validation 139-158 s
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