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BSP Developer's Guide

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VxWorks 5.5<br />

<strong>BSP</strong> Developer’s <strong>Guide</strong><br />

4.3.1 RAM<br />

VxWorks CISC processors require 1 MB of RAM for a development system that<br />

includes all of the standard VxWorks features, such as the shell, network, file<br />

system, loader, and others. RISC processors typically require more RAM space:<br />

2 MB of RAM is the minimum; 4 MB is encouraged. For a scaled-down production<br />

system, the amount of RAM required depends on the application size and the<br />

options selected.<br />

The primary configuration values controlling the usage of memory are<br />

LOCAL_MEM_LOCAL_ADRS, LOCAL_MEM_SIZE, USER_RESERVED_MEM,<br />

ROM_TEXT_ADRS, ROM_WARM_ADRS, and ROM_SIZE. For more information on<br />

these values, see 2.2.1 <strong>BSP</strong> Source and Include Files, p.12.<br />

4.3.2 ROM<br />

VxWorks CISC processors require a minimum of 128 KB of ROM, which is just<br />

sufficient for VxWorks compressed boot ROMs. RISC processors typically require<br />

greater ROM space; 256 KB of ROM should be considered a minimum. These<br />

figures do not include any ROM-resident application code.<br />

Applications running out of ROM are usually slow because of 16-bit or (more<br />

commonly) 8-bit data width, slow access times, and so on. VxWorks avoids this<br />

problem by typically copying the contents of the boot ROMs into RAM.<br />

For information on creating a ROM-resident VxWorks image, see the discussion of<br />

executing VxWorks from ROM in the VxWorks Programmer’s <strong>Guide</strong>: Configuration,<br />

and the Tornado User’s <strong>Guide</strong>: Cross-Development.<br />

The configuration macros ROM_TEXT_ADRS and ROM_SIZE control the actual<br />

usage of ROM memory space. For more information, see 2.2.1 <strong>BSP</strong> Source and<br />

Include Files, p.12.<br />

The macro ROM_WARM_ADRS is the warm boot entry point used by the<br />

sysToMonitor( ) routine. It is normally defined as a constant offset, normally 8<br />

bytes, above the cold boot entry point ROM_TEXT_ADRS.<br />

4.3.3 Ethernet RAM<br />

Some application designers have elected to provide dedicated pools of memory to<br />

DMA-based Ethernet chips. CPU access to its own memory is therefore<br />

unimpeded by incoming Ethernet packets, thus guaranteeing real-time response.<br />

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