BSP Developer's Guide

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VxWorks 5.5 BSP Developer’s Guide Power Usage Extractors VLSI Chips The VMEbus standard specifies the maximum power draw per voltage level. Designers must adhere to these restrictions or clearly document additional power requirements. The typical maximum power consumption per board is about 7 watts. Boards that have requirements in excess of this should emphasize it. VME boards should have card extractors mounted on the front panel. A number of VLSI chips exist that offer complete VMEbus interface functionality. Multibus II This section discusses issues for the BSP developer using Multibus II. Multibus II Specification Multibus II is actually a collection of bus standards: ■ ■ ■ ■ IPSB. a message-passing bus for communication between boards, using geographical addressing ILBX. a memory expansion bus ISBX. a definition for modules that can be plugged into Multibus II boards Multibus II Transport Protocol Specification (Intel) ■ Multibus II Interconnect Interface Specification (Intel) Configuration There are four address spaces on the bus: memory, I/O, message, and interconnect. Multibus II boards do not use DIP switches or jumpers for configuration. Configuration options are set by accessing the target board’s MB II interconnect space. Typical options are memory-board start and end addresses. 74
4 Hardware Guidelines Hardware Interrupts Hardware bus interrupts are not used. Instead, messages are used to convey information (such as device ready) or the actual I/O data. Message passing provides a reliable and easily expandable means of sending information between Multibus II agents. All backplane communications between agents can be handled with messages. No master/slave memory interfaces are required – in fact, memory interfaces are discouraged for use in communicating between boards. Because messages contain data, a block of I/O data can be transferred in the same message as the status or attention information. No memory addressing conflicts arise on the bus and there are no bus memory caching problems because messages are sent between agents, not memory addresses. 4 Processor Number Initialization Multibus boards are slot independent. At system initialization, the system controller (slot 0) sends slot ID numbers to each board. The initialization software on each board then sets up message IDs. During initialization, any or all boards can use the interconnect space to locate specific boards on the bus. For example, each device driver can search the bus for boards that it “recognizes” and can control. This method allows board types and locations and the system configuration to be determined at run time. Interconnect registers and the data contained in interconnect records are defined by Intel. Vendors who comply with the Intel specification identify themselves (via interconnect data) as compliant. Non-compliant boards may be used; such boards identify themselves as non-compliant. Message Passing Protocol Device Drivers Intel has defined a transport protocol for use in sending messages; this protocol is used by many board vendors. This makes adding new device devices easy because the basic communication between agents uses existing message passing routines and conventions. There is usually no hardware-specific code that needs to be written to add a new device once the initial message-passing driver is in place. A BSP normally includes one hardware device driver for the MPC chip (message passing coprocessor) and a transport software module. All VxWorks I/O device drivers send or receive messages by communicating on a software level with the transport layer (or directly with the MPC driver, if necessary). The transport layer 75
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VxWorks® 5.5 BSP DEVELOPER’S GUI
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1 Overview ........................
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Contents 1 Overview ...............
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Contents 3.6.5 Cache, MMU, and DMA
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Contents Memory-Mapped Chips ......
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Contents 7.3.3 System Configuration
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Contents 9.5.4 Processing .........
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Contents F Generic Drivers ........
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Contents Stopping the Driver Withou
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1 Overview 1.1 Introduction One str
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1 Overview ■ New Drivers Many new
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1 Overview Included with Tornado (n
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1 Overview ■ ■ ■ ■ ■ ■
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1 Overview Table 1-1 Font Usage for
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2 BSP Organization 2.1 Introduction
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2 BSP Organization Files in the tar
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2 BSP Organization Files in the tar
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2 BSP Organization Version 1.0 BSPs
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2 BSP Organization SM_MEM_SIZE The
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2 BSP Organization For boards witho
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Page 129 and 130: 6 Components 6.1 Introduction Torna
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6 Components In the example, the co
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6 Components (2) comps/vxWorks/arch
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6 Components Figure 6-4 Include Com
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6 Components NOTE: INIT_BEFORE only
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6 Components The _CHILDREN property
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6 Components ! CAUTION: Do not alte
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6 Components ■ Check the Project
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7 Validation Testing 7.1 Introducti
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7 Validation Testing ■ ■ The te
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7 Validation Testing 2. The script
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7 Validation Testing Figure 7-4 Typ
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7 Validation Testing NOTE: Wind Riv
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7 Validation Testing scsi Requires
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7 Validation Testing Table 7-1 Vali
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7 Validation Testing Table 7-2 Vali
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7 Validation Testing sysProcNumGet
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7 Validation Testing The log file c
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8 Writing Portable C Code This chap
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8 Writing Portable C Code attribute
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8 Writing Portable C Code 8.1.3 Sta
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8 Writing Portable C Code 8.1.5 Oth
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8 Writing Portable C Code The last
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8 Writing Portable C Code Always sp
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8 Writing Portable C Code 8.2 Tool
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9 Documentation Guidelines 9.1 Intr
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9 Documentation Guidelines Spelling
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9 Documentation Guidelines Table 9-
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9 Documentation Guidelines Table 9-
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9 Documentation Guidelines ■ Avoi
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9 Documentation Guidelines ■ ■
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9 Documentation Guidelines INCLUDE
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9 Documentation Guidelines INTRODUC
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9 Documentation Guidelines 9.5 Gene
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9 Documentation Guidelines uppercas
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9 Documentation Guidelines The foll
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10 Product Packaging 10.1 SETUP Dev
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10 Product Packaging ... include $(
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10 Product Packaging Vendor-Supplie
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10 Product Packaging in the project
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A Upgrading a BSP for Tornado 2.0 T
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A Upgrading a BSP for Tornado 2.0 A
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A Upgrading a BSP for Tornado 2.0
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A Upgrading a BSP for Tornado 2.0 6
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B Upgrading a BSP for Tornado 2.2 T
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B Upgrading a BSP for Tornado 2.2 C
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B Upgrading a BSP for Tornado 2.2
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B Upgrading a BSP for Tornado 2.2 c
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B Upgrading a BSP for Tornado 2.2
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C Upgrading a BSP for the VxWorks N
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D VxWorks Boot Sequence Table D-1 d
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D VxWorks Boot Sequence Table D-1 V
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E Component Language E.1 Component
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E Component Language REQUIRES r1 r2
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E Component Language } // default i
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E Component Language FOLDER_WINDVIE
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E Component Language initialization
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E Component Language INCLUDE_MMU_BA
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E Component Language INCLUDE_NETWOR
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E Component Language INCLUDE_WDB_ME
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F Generic Drivers F.1 Introduction
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F Generic Drivers CONSOLE_TTY This
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F Generic Drivers Define SIO_CALLBA
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F Generic Drivers NV_RAM_SIZE Defin
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F Generic Drivers F.10 PCI Bus The
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G Upgrading 4.3 BSD Network Drivers
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H Implementing a MUX-Based Network
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I Writing a SCSI-2 Device Driver I.
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I Writing a SCSI-2 Device Driver On
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I Writing a SCSI-2 Device Driver A
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I Writing a SCSI-2 Device Driver *
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J BSP Validation Test Suite Referen
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K BSP Validation Checklists This ap
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K BSP Validation Checklists BSP Val
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K BSP Validation Checklists 7. Veri
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K BSP Validation Checklists 2. If t
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K BSP Validation Checklists Validat
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K BSP Validation Checklists Manufac
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K BSP Validation Checklists Manufac
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L Refgen NOTE: In Tornado 1.0.1 and
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L Refgen * SYNOPSIS * \cs * void xx
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L Refgen Yields output approximatel
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L Refgen EXAMPLE INCLUDES SEE ALSO
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M BSP Product Contents When you are
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M BSP Product Contents Do not inclu
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Index A abort button 82 addressing
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Index clocks see also individual cl
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Index naming conventions 95 perform
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Index INCLUDE_USR_APPL 38 INCLUDE_V
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Index network drivers 58 network in
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Index scsiCtrlLib 324 scsiDirectLib
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Index testing, validation 139-158 s
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