BSP Developer's Guide

VxWorks 5.5
BSP Developer’s Guide
Before proceeding, determine if the device is DMA capable. Is the device capable of
performing read or write accesses directly to memory that is shared with the CPU?
If the answer is no, your driver might not need any of the cache-related facilities of
the cacheLib. Cache issues affect only those devices that can access memory
shared with the CPU.
If the CPU architecture performs buffered writes, then you might need to deal with
WRITE_PIPING even if the device does not include DMA. Device registers that are
memory mapped should not be cached. In most hardware cases, there is a
hardware mechanism provided that keeps I/O addresses from being cached.
However, keep in mind that even a non-DMA type of device can still have issues
related to write pipelining (see Driver Attributes, p.105).
Shared Memory Types
For DMA-type devices, the driver and the device share one or more memory
regions. This shared memory can be of one of the following types:
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Memory that is allocated using the cacheDmaMalloc( ) routine. This memory
is associated with the CACHE_DMA_xxxx macros and is under the control of
the driver and the underlying hardware for cache issues.
Memory that is allocated using the malloc( ) or memalign( ) routine or
declared in the data or bss sections of the module (stack memory must never
be shared with a device). This type of memory is associated with the
CACHE_DRV_xxxx macros and is solely under the control of the driver for
cache issues.
Because you cannot control the positioning of data obtained by these methods,
this type of memory has an inherent problem: the possibility of sharing a cache
line with an adjacent region that does not belong to the driver. This means that
flush and invalidate operations within this region can interfere with the
coherency of the neighbor’s data in the shared cache lines. Therefore, restrict
the use of this type of memory to exclude the first and last cache line in the
region. Because the cache line size varies on different systems, this becomes a
portability issue.
By using memalign( ), it is possible to insure that buffers are cache line aligned
at their starting address. If you need to protect the end of the buffer, you
should increase the size of this request by at least one cache line size. This
insures that the end of the buffer does not share a cache line with any another
buffer.
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