BSP Developer's Guide

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VxWorks 5.5 BSP Developer’s Guide 4.3.7 Bus This section describes issues of concern when considering the following bus types: ■ ■ ■ ■ VMEbus Multibus II PCI, cPCI, and PMC busless VMEbus This section discusses issues of concern to the BSP developer considering the VMEbus. VME Specification C.1. Addressing VME interoperability is crucial for the success of the standard. Special-purpose extensions to the bus should be confined to the user pins on rows A and C of the P2, and they should be clearly documented. Under no circumstance is it acceptable to deviate from the timings presented in the specification. The VME-64 Specification is a superset of earlier specifications. At this time Wind River does not provide support for the plug and play features provided in the VME-64 specification or any of its extensions. The choice of address map is not critical in VxWorks. Local addresses can obscure parts of the VME bus address space. Some boards cannot address low memory on the bus because their local address starts at 0. This is not a problem for VxWorks, because all VME device drivers are configurable. However, conflicting devices may be a system issue. Dynamic Bus Sizing on VMEbus Accesses There are three address types defined in the specification: ■ A16 short ■ A24 standard ■ A32 extended In addition, there are often data width restrictions to off-board devices. Many implementers offer different windows with different data widths (D16 or D32) to the same VME address. 70
4 Hardware Guidelines Especially useful are windows that break the wider D32 accesses into two D16 accesses automatically. This can be achieved with the dynamic bus-sizing capability of some architectures (for example, 68K). Some boards require that a register be initialized to indicate data “direction” (read/write) in addition to the AM (Address Modifier). This is inconvenient. See config.h, p.16, for a standard set of configuration macros to declare master and slave access windows onto the VMEbus. Wind River does not provide direct support of 64-bit addressing or data. However, this does not preclude board specific routines from providing such support to the user. 4 Dual-Port Memory RMW Most CPU boards have local (on-board) RAM. Creating a slave access window on the VMEbus makes the local memory accessible by other CPUs and DMA devices on the bus. This is also called dual porting. It is required by systems that want backplane-shared memory to be on the local processor’s RAM. Such dual-ported memory should fully support RMW cycles as described below. Dual porting is also required for off board devices that DMA into target memory, such as the Excelan EXOS-302. It is useful if the dual-ported memory can be seen by the local processor at the memory’s external address, although this is often not provided (and is not used by VxWorks). Dual-port memory is also very useful during porting; it facilitates the use of backplane debugging. Read-modify-write (RMW) must be provided in an indivisible manner. The board must adhere to the RMW mechanism defined in the VME specification; namely, a master must keep the address strobe low between the read and the write portions of the cycle. A correctly functioning dual-ported slave board keeps the RMW indivisible across both ports by detecting an address strobe that remains low. Unfortunately, keeping the address strobe low is only viable if you are reading and writing the same single address. A more complicated indivisible instruction, such as CAS, that involves multiple addresses cannot use this, and thus has no correct mechanism for dual-ported memory. Because VxWorks uses only TAS, this is not an issue. Some vendors have added a LOCK pin to the P2 bus for this reason. 71
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VxWorks® 5.5 BSP DEVELOPER’S GUI
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1 Overview ........................
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Contents 1 Overview ...............
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Contents 3.6.5 Cache, MMU, and DMA
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Contents Memory-Mapped Chips ......
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Contents 7.3.3 System Configuration
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Contents 9.5.4 Processing .........
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Contents F Generic Drivers ........
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Contents Stopping the Driver Withou
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1 Overview 1.1 Introduction One str
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1 Overview ■ New Drivers Many new
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1 Overview Included with Tornado (n
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1 Overview ■ ■ ■ ■ ■ ■
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1 Overview Table 1-1 Font Usage for
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2 BSP Organization 2.1 Introduction
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2 BSP Organization Files in the tar
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2 BSP Organization Files in the tar
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2 BSP Organization Version 1.0 BSPs
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Page 129 and 130: 6 Components 6.1 Introduction Torna
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6 Components The component object i
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6 Components Parameters Parameters
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6 Components In the example, the co
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6 Components (2) comps/vxWorks/arch
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6 Components Figure 6-4 Include Com
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6 Components NOTE: INIT_BEFORE only
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6 Components The _CHILDREN property
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6 Components ! CAUTION: Do not alte
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6 Components ■ Check the Project
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7 Validation Testing 7.1 Introducti
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7 Validation Testing ■ ■ The te
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7 Validation Testing 2. The script
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7 Validation Testing Figure 7-4 Typ
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7 Validation Testing NOTE: Wind Riv
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7 Validation Testing scsi Requires
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7 Validation Testing Table 7-1 Vali
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7 Validation Testing Table 7-2 Vali
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7 Validation Testing sysProcNumGet
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7 Validation Testing The log file c
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8 Writing Portable C Code This chap
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8 Writing Portable C Code attribute
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8 Writing Portable C Code 8.1.3 Sta
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8 Writing Portable C Code 8.1.5 Oth
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8 Writing Portable C Code The last
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8 Writing Portable C Code Always sp
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8 Writing Portable C Code 8.2 Tool
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9 Documentation Guidelines 9.1 Intr
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9 Documentation Guidelines Table 9-
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9 Documentation Guidelines Table 9-
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9 Documentation Guidelines INCLUDE
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9 Documentation Guidelines INTRODUC
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9 Documentation Guidelines 9.5 Gene
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9 Documentation Guidelines The foll
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10 Product Packaging 10.1 SETUP Dev
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10 Product Packaging ... include $(
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10 Product Packaging Vendor-Supplie
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10 Product Packaging in the project
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A Upgrading a BSP for Tornado 2.0 T
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A Upgrading a BSP for Tornado 2.0 A
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A Upgrading a BSP for Tornado 2.0
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A Upgrading a BSP for Tornado 2.0 6
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B Upgrading a BSP for Tornado 2.2 T
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B Upgrading a BSP for Tornado 2.2 C
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B Upgrading a BSP for Tornado 2.2
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B Upgrading a BSP for Tornado 2.2 c
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B Upgrading a BSP for Tornado 2.2
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C Upgrading a BSP for the VxWorks N
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D VxWorks Boot Sequence Table D-1 d
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D VxWorks Boot Sequence Table D-1 V
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E Component Language E.1 Component
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E Component Language REQUIRES r1 r2
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E Component Language FOLDER_WINDVIE
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E Component Language initialization
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E Component Language INCLUDE_MMU_BA
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E Component Language INCLUDE_NETWOR
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E Component Language INCLUDE_WDB_ME
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F Generic Drivers F.1 Introduction
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F Generic Drivers CONSOLE_TTY This
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F Generic Drivers Define SIO_CALLBA
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F Generic Drivers NV_RAM_SIZE Defin
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F Generic Drivers F.10 PCI Bus The
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G Upgrading 4.3 BSD Network Drivers
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H Implementing a MUX-Based Network
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I Writing a SCSI-2 Device Driver I.
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J BSP Validation Test Suite Referen
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K BSP Validation Checklists This ap
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K BSP Validation Checklists BSP Val
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K BSP Validation Checklists 7. Veri
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K BSP Validation Checklists 2. If t
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K BSP Validation Checklists Validat
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K BSP Validation Checklists Manufac
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K BSP Validation Checklists Manufac
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L Refgen NOTE: In Tornado 1.0.1 and
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L Refgen * SYNOPSIS * \cs * void xx
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L Refgen Yields output approximatel
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L Refgen EXAMPLE INCLUDES SEE ALSO
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M BSP Product Contents When you are
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M BSP Product Contents Do not inclu
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Index A abort button 82 addressing
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Index clocks see also individual cl
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Index naming conventions 95 perform
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Index INCLUDE_USR_APPL 38 INCLUDE_V
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Index network drivers 58 network in
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Index scsiCtrlLib 324 scsiDirectLib
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Index testing, validation 139-158 s
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