Full-Custom Layout of an SRAM-Based FPGA - University of Toronto

2. Tile Block Diagram
The following figure shows the block diagram of one tile with interfaces of basic
building blocks in our design. The logic element (LE) evaluates a logic function of its
inputs, and produces the result on its output. Both inputs and outputs are connected to the
routing tracks through the programmable switches in connection boxes. There are two
connection boxes in a tile. Connection_box_bottom connects the inputs of the LEs above
and below it, as well as the output of the LE above it, to the routing tracks. Similarly,
connection_box_right connects the inputs of the LEs left and right from it to the routing
tracks. The horizontal and vertical routing tracks are interconnected inside a switch box.
Although the programming logic is not a part of the tile, it is shown here for
completeness. The programming logic is used to program SRAM cells in the tile.