Full-Custom Layout of an SRAM-Based FPGA - University of Toronto

Caculate SRAMs in logic Block:
Logic Block contains 19 total SRAMs as seen below:
4 LUT
16 SRAMS
D Flip
Flop
Set
Reset
Logic
1 SRAM
2 SRAM
Total SRAMs for each tile = 19 (from Logic) + 6 (from C1) + 8 (from C2) + 12 (from S)
= 45 SRAMs
b. Area Calculations:
Area estimations of SRAM cells
From stick diagram, there are 9 vertical lines and 7 horizontal lines
Thus:
A = W x H
= (9 x 4) λ x (7 x 4) λ
= 36 λ x 28 λ
= 7.2 um x 5.6 um
= 40.32 um 2
Area estimations of DFlipFlop
From stick diagram, there are 24 vertical lines and 6 horizontal lines
Thus
A = W x H
= (24 x 4) λ x (6 x 4) λ
= 96 λ x 24 λ
= 19.2 um x 4.8 um
= 92.16 um 2
S Block approx area: 12 SRAMs x 40.32 um 2 = 483.84 um 2
Logic Block area: (not estimates for devices below were obtained from Appendix B of
“Architecture and CAD for Deep-Submicron FPGAs)
A = 1 Dreg + 1 2-1Multiplexer + 1 4 Lut + 1 Set/Rest logic