Full-Custom Layout of an SRAM-Based FPGA - University of Toronto

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Logic Element The Logic Element cell was designed using 3 main components as seen in the schematic figure below. The 3 elements are a 4 variable look up table, a register, and a mux to select between a registered and a non-registered output. It is designed in a hierarchal manner as all components are instances of smaller levels of design. The area taken up by the logic element is 64.75u x 61.6u (hxw) as seen in the layout figure below. It was designed to align with the bottom and right connection blocks. Logic Element Schematic Figure Logic Element Layout Figure
Connection Bottom Block The Connection Bottom block cell was designed to connect to logic elements located above and below to the routing tracks. It is designed in a hierarchal manner as all components are instances of smaller levels of design as seen the schematic figure below. The area taken up by the connection bottom block is 37u x 61.2u (h x w) as seen in the layout figure below. It was designed to align with the logic element block as well as with the switch block. Connection Bottom Block Schematic Figure Connection Bottom Block Layout Figure
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UNIVERSITY OF TORONTO ECE1388 VLSI
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There has been a great deal of stud
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The final design contains 48 pins.
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[1] V. Betz, J. Rose, and A. Marqua
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1. FPGA Design The purpose of this
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3. Logic Element The logic element
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4. Routing Routing consists of the
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5. Programming Circuitry We are goi
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Caculate SRAMs in logic Block: Logi
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Appendix C Cell Circuit Design Repo
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Each wire is connected to another t
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There are two new components in thi
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Pass transistors that connect outpu
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Since this connection box only cont
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Feedback Buffer: The feedback buffe
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The following two circuits are the
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NAND:
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The following two figures the circu
Page 41 and 42: Schematic Description of program_ro
Page 43 and 44: Figure 2: program_col Schematic Fig
Page 45 and 46: Figure 5: Clock Input to program_ro
Page 47 and 48: Figure 9: Output of Program Figure
Page 53 and 54: Figure 21: Output of Program_data F
Page 55 and 56: Appendix D Full Schematic Design Re
Page 57 and 58: To test the individual tile, and th
Page 59 and 60: To test the tile, we implement the
Page 61: The first figure shows the programm
Page 64 and 65: The three by three array of tiles c
Page 66 and 67: tiles, and then an array of four by
Page 68 and 69: Appendix E Layout of the Cells Repo
Page 70 and 71: The SRAM cell is one our base cells
Page 72 and 73: Switch box interconnects the wiring
Page 74 and 75: Inverters are standard design, as w
Page 76 and 77: 4-to-1 multiplexer is made out of 3
Page 78 and 79: Connection Box Bottom Connection bo
Page 80 and 81: The Input_to_LE cell was designed u
Page 82 and 83: All the cells passed DRC and LVS. H
Page 84 and 85: connection_box_right: @(#)$CDS: LVS
Page 86 and 87: connect_box_bottom: @(#)$CDS: LVS v
Page 88 and 89: Switchbox: @(#)$CDS: LVS version 4.
Page 90 and 91: prunenet.out: prunedev.out: audit.o
Page 94 and 95: Connection Right Block The Connecti
Page 96 and 97: Switch Block Layout Figure Tile Blo
Page 98 and 99: Program Row Tile Block The Program
Page 100 and 101: Program Column Tile Block The Progr
Page 103 and 104: FPGA Top-Level Schematic:
Page 105 and 106: The net-lists match. layout schemat
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Full-Custom Layout of an SRAM-Based FPGA - University of Toronto

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