Full-Custom Layout of an SRAM-Based FPGA - University of Toronto

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Appendix A List of References
[1] V. Betz, J. Rose, and A. Marquardt, Architecture and CAD for Deep-Submicron FPGAs, Kluwer Academic Publishers: Norwell, MA, 1999. [2] N. H. E. Weste, D. Harris. CMOS VLSI Design: A Circuits and Systems Perspective, 3 rd ed., Pearson Addison Wesley, Boston MA, 2005 [3] Chow, P., S. Seo, J. Rose, K. Chung, G. Pez-Monzn and I. Rahardja. "The Design of an SRAM-Based Field-Programmable Gate Array, Part I: Architecture", IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 7 No. 2, June. 1999, pp. 191-197 [4] Chow, P., S. Seo, J. Rose, K. Chung, G. Pez-Monzn and I. Rahardja. "The Design of an SRAM-Based Field-Programmable Gate Array, Part II: Circuit Design and Layout", IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 7 No. 3, Sept. 1999, pp. 321-330 [5] V. Betz and J. Rose, Segmentation and Buffering to Optimize Speed and Density, In Proceedings of FPGA ‘99, Monterey, CA, 1999, pp 59 – 68
Page 1 and 2: UNIVERSITY OF TORONTO ECE1388 VLSI
Page 3 and 4: There has been a great deal of stud
Page 5: The final design contains 48 pins.
Page 9 and 10: 1. FPGA Design The purpose of this
Page 12 and 13: 3. Logic Element The logic element
Page 15 and 16: 4. Routing Routing consists of the
Page 18 and 19: 5. Programming Circuitry We are goi
Page 20 and 21: Caculate SRAMs in logic Block: Logi
Page 22 and 23: Appendix C Cell Circuit Design Repo
Page 24 and 25: Each wire is connected to another t
Page 26 and 27: There are two new components in thi
Page 28 and 29: Pass transistors that connect outpu
Page 30 and 31: Since this connection box only cont
Page 32 and 33: Feedback Buffer: The feedback buffe
Page 34 and 35: The following two circuits are the
Page 36 and 37: NAND:
Page 38 and 39: The following two figures the circu
Page 41 and 42: Schematic Description of program_ro
Page 43 and 44: Figure 2: program_col Schematic Fig
Page 45 and 46: Figure 5: Clock Input to program_ro
Page 47 and 48: Figure 9: Output of Program Figure
Page 53 and 54: Figure 21: Output of Program_data F
Page 55 and 56: Appendix D Full Schematic Design Re
Page 57 and 58:
To test the individual tile, and th
Page 59 and 60:
To test the tile, we implement the
Page 61:
The first figure shows the programm
Page 64 and 65:
The three by three array of tiles c
Page 66 and 67:
tiles, and then an array of four by
Page 68 and 69:
Appendix E Layout of the Cells Repo
Page 70 and 71:
The SRAM cell is one our base cells
Page 72 and 73:
Switch box interconnects the wiring
Page 74 and 75:
Inverters are standard design, as w
Page 76 and 77:
4-to-1 multiplexer is made out of 3
Page 78 and 79:
Connection Box Bottom Connection bo
Page 80 and 81:
The Input_to_LE cell was designed u
Page 82 and 83:
All the cells passed DRC and LVS. H
Page 84 and 85:
connection_box_right: @(#)$CDS: LVS
Page 86 and 87:
connect_box_bottom: @(#)$CDS: LVS v
Page 88 and 89:
Switchbox: @(#)$CDS: LVS version 4.
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prunenet.out: prunedev.out: audit.o
Page 92 and 93:
Logic Element The Logic Element cel
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Connection Right Block The Connecti
Page 96 and 97:
Switch Block Layout Figure Tile Blo
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Program Row Tile Block The Program
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Program Column Tile Block The Progr
Page 103 and 104:
FPGA Top-Level Schematic:
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The net-lists match. layout schemat
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