Full-Custom Layout of an SRAM-Based FPGA - University of Toronto

1. FPGA Design
The purpose of this project is to implement a full custom layout of a simple FPGA
device. The basic building block of an FPGA is logic element (LE), which consists of a
lookup table (LUT), a flip-flop, and a multiplexer that chooses whether to forward the
output of the LUT or the flip-flop outside the LE. A k-LUT consist of a set of
multiplexers that implement any function of k inputs by forwarding one of the 2 k
configuration bits to the output of the LUT. LEs are interconnected with routing
resources which are also configurable. Configuration of routing resources is achieved
using pass gates controlled by a routing configuration bits. The desired configuration is
stored in the SRAM cells. One SRAM cell is required per pass gate, while a k-LUT
requires 2 k SRAM cells.
Since FPGA structure is regular, the design is divided into tiles. Each tile consists of
an LE and routing resources, as shown in the figure below [1]. LEs are labeled with L in
the figure. Routing wires run horizontally and vertically, and may be interconnected
inside switch boxes (S). Logic blocks connect to the routing tracks in the connection
boxes (C). The design proposed in this work was based on the techniques described in [1]
and [2].
The following figure shows the top view of the FPGA that will be implemented. As
can be seen in the figure, the proposed FPGA design has 10 pins for control signals
and 14 pins for general purpose I/O signals. Control signals are clock, which controls
all the flip-flops inside LEs, VDD and GND pins, and programming signals. The
function of these signals will be described in more detail in the following sections.