Full-Custom Layout of an SRAM-Based FPGA - University of Toronto

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connection_box_right: @(#)$CDS: LVS version 4.4.5 04/20/2000 16:37 (cds11182) $ Like matching is enabled. Net swapping is enabled. Using terminal names as correspondence points. Net-list summary for /zvonko/r/r0/fort/cmosp35/LVS/layout/netlist count 51 nets 19 terminals 60 nfet 37 pfet Net-list summary for /zvonko/r/r0/fort/cmosp35/LVS/schematic/netlist count 51 nets 19 terminals 60 nfet 37 pfet Terminal correspondence points 1 left_lb_input 2 prog_data 3 prog_data 4 prog_data 5 prog_data 6 prog_datab 7 prog_datab 8 prog_datab 9 prog_datab 10 program 11 program 12 right_lb_input 13 set_reset 14 track 15 track 16 track 17 track 18 vdd! 19 vss! The net-lists match. layout schematic inst<strong>an</strong>ces un-matched 0 0 rewired 0 0 size errors 0 0 pruned 0 0 active 97 97 total 97 97 nets un-matched 0 0 merged 0 0
pruned 0 0 active 51 51 total 51 51 terminals un-matched 0 0 matched but different type 0 0 total 19 19 Probe files from /zvonko/r/r0/fort/cmosp35/LVS/schematic devbad.out: netbad.out: mergenet.out: termbad.out: prunenet.out: prunedev.out: audit.out: Probe files from /zvonko/r/r0/fort/cmosp35/LVS/layout devbad.out: netbad.out: mergenet.out: termbad.out: prunenet.out: prunedev.out: audit.out:
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UNIVERSITY OF TORONTO ECE1388 VLSI
Page 3 and 4:
There has been a great deal of stud
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The final design contains 48 pins.
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[1] V. Betz, J. Rose, and A. Marqua
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1. FPGA Design The purpose of this
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3. Logic Element The logic element
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4. Routing Routing consists of the
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5. Programming Circuitry We are goi
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Caculate SRAMs in logic Block: Logi
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Appendix C Cell Circuit Design Repo
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Each wire is connected to another t
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There are two new components in thi
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Pass transistors that connect outpu
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Since this connection box only cont
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Feedback Buffer: The feedback buffe
Page 34 and 35: The following two circuits are the
Page 36 and 37: NAND:
Page 38 and 39: The following two figures the circu
Page 41 and 42: Schematic Description of program_ro
Page 43 and 44: Figure 2: program_col Schematic Fig
Page 45 and 46: Figure 5: Clock Input to program_ro
Page 47 and 48: Figure 9: Output of Program Figure
Page 53 and 54: Figure 21: Output of Program_data F
Page 55 and 56: Appendix D Full Schematic Design Re
Page 57 and 58: To test the individual tile, and th
Page 59 and 60: To test the tile, we implement the
Page 61: The first figure shows the programm
Page 64 and 65: The three by three array of tiles c
Page 66 and 67: tiles, and then an array of four by
Page 68 and 69: Appendix E Layout of the Cells Repo
Page 70 and 71: The SRAM cell is one our base cells
Page 72 and 73: Switch box interconnects the wiring
Page 74 and 75: Inverters are standard design, as w
Page 76 and 77: 4-to-1 multiplexer is made out of 3
Page 78 and 79: Connection Box Bottom Connection bo
Page 80 and 81: The Input_to_LE cell was designed u
Page 82 and 83: All the cells passed DRC and LVS. H
Page 86 and 87: connect_box_bottom: @(#)$CDS: LVS v
Page 88 and 89: Switchbox: @(#)$CDS: LVS version 4.
Page 90 and 91: prunenet.out: prunedev.out: audit.o
Page 92 and 93: Logic Element The Logic Element cel
Page 94 and 95: Connection Right Block The Connecti
Page 96 and 97: Switch Block Layout Figure Tile Blo
Page 98 and 99: Program Row Tile Block The Program
Page 100 and 101: Program Column Tile Block The Progr
Page 103 and 104: FPGA Top-Level Schematic:
Page 105 and 106: The net-lists match. layout schemat
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Full-Custom Layout of an SRAM-Based FPGA - University of Toronto

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