Full-Custom Layout of an SRAM-Based FPGA - University of Toronto

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Appendix E Layout of the Cells Report
Layout Figure 1: NAND Gate The nand gate is one our base cells. It is used by modules higher up in the hierarchy. The inputs to our nand gate are labeled A and B and output is labeled out as seen in the figure. The height of our nand gate has been increased to match the pitch of our largest cell. Figure 2: XOR Cell The XOR cell was designed using 4 nand gates as seen in the figure. We designed the XOR with nand gates instead of designing it from transistors to reduce the pitch of the XOR gate. It is designed in a hierarchal manner as 4 instances of nand gates are instantiated and then connected. The XOR cell has 2inputs labeled A and B and one output labeled out as seen in the figure. Figure 3: SRAM Cell
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UNIVERSITY OF TORONTO ECE1388 VLSI
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There has been a great deal of stud
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The final design contains 48 pins.
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[1] V. Betz, J. Rose, and A. Marqua
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1. FPGA Design The purpose of this
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3. Logic Element The logic element
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4. Routing Routing consists of the
Page 18 and 19: 5. Programming Circuitry We are goi
Page 20 and 21: Caculate SRAMs in logic Block: Logi
Page 22 and 23: Appendix C Cell Circuit Design Repo
Page 24 and 25: Each wire is connected to another t
Page 26 and 27: There are two new components in thi
Page 28 and 29: Pass transistors that connect outpu
Page 30 and 31: Since this connection box only cont
Page 32 and 33: Feedback Buffer: The feedback buffe
Page 34 and 35: The following two circuits are the
Page 36 and 37: NAND:
Page 38 and 39: The following two figures the circu
Page 41 and 42: Schematic Description of program_ro
Page 43 and 44: Figure 2: program_col Schematic Fig
Page 45 and 46: Figure 5: Clock Input to program_ro
Page 47 and 48: Figure 9: Output of Program Figure
Page 53 and 54: Figure 21: Output of Program_data F
Page 55 and 56: Appendix D Full Schematic Design Re
Page 57 and 58: To test the individual tile, and th
Page 59 and 60: To test the tile, we implement the
Page 61: The first figure shows the programm
Page 64 and 65: The three by three array of tiles c
Page 66 and 67: tiles, and then an array of four by
Page 70 and 71: The SRAM cell is one our base cells
Page 72 and 73: Switch box interconnects the wiring
Page 74 and 75: Inverters are standard design, as w
Page 76 and 77: 4-to-1 multiplexer is made out of 3
Page 78 and 79: Connection Box Bottom Connection bo
Page 80 and 81: The Input_to_LE cell was designed u
Page 82 and 83: All the cells passed DRC and LVS. H
Page 84 and 85: connection_box_right: @(#)$CDS: LVS
Page 86 and 87: connect_box_bottom: @(#)$CDS: LVS v
Page 88 and 89: Switchbox: @(#)$CDS: LVS version 4.
Page 90 and 91: prunenet.out: prunedev.out: audit.o
Page 92 and 93: Logic Element The Logic Element cel
Page 94 and 95: Connection Right Block The Connecti
Page 96 and 97: Switch Block Layout Figure Tile Blo
Page 98 and 99: Program Row Tile Block The Program
Page 100 and 101: Program Column Tile Block The Progr
Page 103 and 104: FPGA Top-Level Schematic:
Page 105 and 106: The net-lists match. layout schemat
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Full-Custom Layout of an SRAM-Based FPGA - University of Toronto

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