Appendix A List <strong>of</strong> References
[1] V. Betz, J. Rose, <strong>an</strong>d A. Marquardt, Architecture <strong>an</strong>d CAD for Deep-Submicron <strong>FPGA</strong>s, Kluwer Academic Publishers: Norwell, MA, 1999. [2] N. H. E. Weste, D. Harris. CMOS VLSI Design: A Circuits <strong>an</strong>d Systems Perspective, 3 rd ed., Pearson Addison Wesley, Boston MA, 2005 [3] Chow, P., S. Seo, J. Rose, K. Chung, G. Pez-Monzn <strong>an</strong>d I. Rahardja. "The Design <strong>of</strong> <strong>an</strong> <strong>SRAM</strong>-<strong>Based</strong> Field-Programmable Gate Array, Part I: Architecture", IEEE Tr<strong>an</strong>sactions on Very Large Scale Integration (VLSI) Systems, Vol. 7 No. 2, June. 1999, pp. 191-197 [4] Chow, P., S. Seo, J. Rose, K. Chung, G. Pez-Monzn <strong>an</strong>d I. Rahardja. "The Design <strong>of</strong> <strong>an</strong> <strong>SRAM</strong>-<strong>Based</strong> Field-Programmable Gate Array, Part II: Circuit Design <strong>an</strong>d <strong>Layout</strong>", IEEE Tr<strong>an</strong>sactions on Very Large Scale Integration (VLSI) Systems, Vol. 7 No. 3, Sept. 1999, pp. 321-330 [5] V. Betz <strong>an</strong>d J. Rose, Segmentation <strong>an</strong>d Buffering to Optimize Speed <strong>an</strong>d Density, In Proceedings <strong>of</strong> <strong>FPGA</strong> ‘99, Monterey, CA, 1999, pp 59 – 68