Full-Custom Layout of an SRAM-Based FPGA - University of Toronto

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Final LVS Report: @(#)$CDS: LVS version 4.4.5 04/20/2000 16:37 (cds11182) $ Like matching is enabled. Net swapping is enabled. Using terminal names as correspondence points. Net-list summary for /zvonko/r/r0/plavec/ece1388/chapter3/LVS/layout/netlist count 54086 nets 46 terminals 91364 nfet 88 diode 51825 pfet Net-list summary for /zvonko/r/r0/plavec/ece1388/chapter3/LVS/schematic/netlist count 54086 nets 46 terminals 91364 nfet 88 diode 51825 pfet Terminal correspondence points 1 clock 2 col_clk 3 in0 4 in1 5 in10 6 in11 7 in12 8 in13 9 in14 10 in15 11 in16 12 in17 13 in18 14 in2 15 in3 16 in4 17 in5 18 in6 19 in7 20 in8 21 in9 22 out0 23 out1 24 out10 25 out11 26 out12 27 out13 28 out14 29 out15 30 out16 31 out17 32 out18 33 out2 34 out3 35 out4 36 out5 37 out6 38 out7 39 out8 40 out9 41 program_data_col 42 program_data_row 43 program_enable 44 row_clk 45 vdd! 46 vss!
The net-lists match. layout schematic inst<strong>an</strong>ces un-matched 0 0 rewired 0 0 size errors 0 0 pruned 0 0 active 143277 143277 total 143277 143277 nets un-matched 0 0 merged 0 0 pruned 0 0 active 54086 54086 total 54086 54086 terminals un-matched 0 0 matched but different type 0 0 total 46 46 Probe files from /zvonko/r/r0/plavec/ece1388/chapter3/LVS/schematic devbad.out: netbad.out: mergenet.out: termbad.out: prunenet.out: prunedev.out: audit.out: Probe files from /zvonko/r/r0/plavec/ece1388/chapter3/LVS/layout devbad.out: netbad.out: mergenet.out: termbad.out: prunenet.out: prunedev.out: audit.out:
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UNIVERSITY OF TORONTO ECE1388 VLSI
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There has been a great deal of stud
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The final design contains 48 pins.
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[1] V. Betz, J. Rose, and A. Marqua
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1. FPGA Design The purpose of this
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3. Logic Element The logic element
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4. Routing Routing consists of the
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5. Programming Circuitry We are goi
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Caculate SRAMs in logic Block: Logi
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Appendix C Cell Circuit Design Repo
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Each wire is connected to another t
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There are two new components in thi
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Pass transistors that connect outpu
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Since this connection box only cont
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Feedback Buffer: The feedback buffe
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The following two circuits are the
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NAND:
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The following two figures the circu
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Schematic Description of program_ro
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Figure 2: program_col Schematic Fig
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Figure 5: Clock Input to program_ro
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Figure 9: Output of Program Figure
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Page 53 and 54: Figure 21: Output of Program_data F
Page 55 and 56: Appendix D Full Schematic Design Re
Page 57 and 58: To test the individual tile, and th
Page 59 and 60: To test the tile, we implement the
Page 61: The first figure shows the programm
Page 64 and 65: The three by three array of tiles c
Page 66 and 67: tiles, and then an array of four by
Page 68 and 69: Appendix E Layout of the Cells Repo
Page 70 and 71: The SRAM cell is one our base cells
Page 72 and 73: Switch box interconnects the wiring
Page 74 and 75: Inverters are standard design, as w
Page 76 and 77: 4-to-1 multiplexer is made out of 3
Page 78 and 79: Connection Box Bottom Connection bo
Page 80 and 81: The Input_to_LE cell was designed u
Page 82 and 83: All the cells passed DRC and LVS. H
Page 84 and 85: connection_box_right: @(#)$CDS: LVS
Page 86 and 87: connect_box_bottom: @(#)$CDS: LVS v
Page 88 and 89: Switchbox: @(#)$CDS: LVS version 4.
Page 90 and 91: prunenet.out: prunedev.out: audit.o
Page 92 and 93: Logic Element The Logic Element cel
Page 94 and 95: Connection Right Block The Connecti
Page 96 and 97: Switch Block Layout Figure Tile Blo
Page 98 and 99: Program Row Tile Block The Program
Page 100 and 101: Program Column Tile Block The Progr
Page 103: FPGA Top-Level Schematic:
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Full-Custom Layout of an SRAM-Based FPGA - University of Toronto

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