Full-Custom Layout of an SRAM-Based FPGA - University of Toronto

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Caculate SRAMs in logic Block: Logic Block contains 19 total SRAMs as seen below: 4 LUT 16 SRAMS D Flip Flop Set Reset Logic 1 SRAM 2 SRAM Total SRAMs for each tile = 19 (from Logic) + 6 (from C1) + 8 (from C2) + 12 (from S) = 45 SRAMs b. Area Calculations: Area estimations of SRAM cells From stick diagram, there are 9 vertical lines and 7 horizontal lines Thus: A = W x H = (9 x 4) λ x (7 x 4) λ = 36 λ x 28 λ = 7.2 um x 5.6 um = 40.32 um 2 Area estimations of DFlipFlop From stick diagram, there are 24 vertical lines and 6 horizontal lines Thus A = W x H = (24 x 4) λ x (6 x 4) λ = 96 λ x 24 λ = 19.2 um x 4.8 um = 92.16 um 2 S Block approx area: 12 SRAMs x 40.32 um 2 = 483.84 um 2 Logic Block area: (not estimates for devices below were obtained from Appendix B of “Architecture and CAD for Deep-Submicron FPGAs) A = 1 Dreg + 1 2-1Multiplexer + 1 4 Lut + 1 Set/Rest logic
= 92.16 um 2 + (8 x unit size trans) +(30 x unit size trans) +(48.5 x unit size trans) = 92.16 + (8 + 30 + 48.5)3.75 =1182.62um 2 The C Blocks can fit into the measurement sizes the result from the S Block and Logic Block. Determining The Tile Area Size Thus: The Logic block can be fit into 35um x 35 um block The Switch block can be fit into 22um x 22um block Thus the tile size required is approx 60um x 60 um. Since we need to program 45 SRAMS, we choose to make the tile size: W x H = 80 um x 60 um This is necessary to fit the program circuitry required for each tile as described in the section “Programming Circuitry”. Since each DFlipFlop requires a width of 20 um, and we need 4 per tile width, we need the tile width to be at least 80 um. According to these estimations, we estimate that we will be able to fit 11 rows X 9 columns of tiles into the area available after the area consumed by I/O pads is taken into account.
Page 1 and 2: UNIVERSITY OF TORONTO ECE1388 VLSI
Page 3 and 4: There has been a great deal of stud
Page 5 and 6: The final design contains 48 pins.
Page 7 and 8: [1] V. Betz, J. Rose, and A. Marqua
Page 9 and 10: 1. FPGA Design The purpose of this
Page 12 and 13: 3. Logic Element The logic element
Page 15 and 16: 4. Routing Routing consists of the
Page 18 and 19: 5. Programming Circuitry We are goi
Page 22 and 23: Appendix C Cell Circuit Design Repo
Page 24 and 25: Each wire is connected to another t
Page 26 and 27: There are two new components in thi
Page 28 and 29: Pass transistors that connect outpu
Page 30 and 31: Since this connection box only cont
Page 32 and 33: Feedback Buffer: The feedback buffe
Page 34 and 35: The following two circuits are the
Page 36 and 37: NAND:
Page 38 and 39: The following two figures the circu
Page 41 and 42: Schematic Description of program_ro
Page 43 and 44: Figure 2: program_col Schematic Fig
Page 45 and 46: Figure 5: Clock Input to program_ro
Page 47 and 48: Figure 9: Output of Program Figure
Page 53 and 54: Figure 21: Output of Program_data F
Page 55 and 56: Appendix D Full Schematic Design Re
Page 57 and 58: To test the individual tile, and th
Page 59 and 60: To test the tile, we implement the
Page 61: The first figure shows the programm
Page 64 and 65: The three by three array of tiles c
Page 66 and 67: tiles, and then an array of four by
Page 68 and 69: Appendix E Layout of the Cells Repo
Page 70 and 71:
The SRAM cell is one our base cells
Page 72 and 73:
Switch box interconnects the wiring
Page 74 and 75:
Inverters are standard design, as w
Page 76 and 77:
4-to-1 multiplexer is made out of 3
Page 78 and 79:
Connection Box Bottom Connection bo
Page 80 and 81:
The Input_to_LE cell was designed u
Page 82 and 83:
All the cells passed DRC and LVS. H
Page 84 and 85:
connection_box_right: @(#)$CDS: LVS
Page 86 and 87:
connect_box_bottom: @(#)$CDS: LVS v
Page 88 and 89:
Switchbox: @(#)$CDS: LVS version 4.
Page 90 and 91:
prunenet.out: prunedev.out: audit.o
Page 92 and 93:
Logic Element The Logic Element cel
Page 94 and 95:
Connection Right Block The Connecti
Page 96 and 97:
Switch Block Layout Figure Tile Blo
Page 98 and 99:
Program Row Tile Block The Program
Page 100 and 101:
Program Column Tile Block The Progr
Page 103 and 104:
FPGA Top-Level Schematic:
Page 105 and 106:
The net-lists match. layout schemat
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