Full-Custom Layout of an SRAM-Based FPGA - University of Toronto

More documents

Recommendations

Info

3. Logic Element The logic element is the computational block of the FPGA. This is where an arbitrary function can be applied to the input signals to produce a specific result. Figure 1 is the top level view of the logic element. The logic element consists of three subblocks: a LUT, a register and a 2 to 1 mux, as seen in Figure 2. Figure 1: Top level view of the logic element. Figure 2: Internal view of Logic Element The lookup-table (LUT), as seen in Figure 3, is used to create the result of the desired arbitrary function. LUTs are choosen because at the time of fabrication of the FPGA it is unknown what functions the ended user of the FPGA will want, and LUTs are the simplest and smallest way to provide the functional for allowing arbitrary function to be programmed. Since we will be using 4 inputs LUTs, each LUT will need 16 (2 4 ) sram cells (it’s 2 4 because each input can have two values [0 or 1] and there are 4 inputs. The sram cells are to be programmed will the 16 possible results of the arbitrary functions.
Figure 3: Lockup-Table (LUT) The register, as seen in figure 4, allows the output of the logic to be used as an input to that logic or a previous logic block without causing a combination loop. A combination loop is when the output affects the inputs, which in turn causes the output to change, which affects the input, and so on, never reaching a steady state, which means the output is unpredictable. Another use of the register is to allow for pipelined designs, which can increase the throughput of the function programmed to the FPGA. Figure 4: Register The final element in the logic block is a multiplexer. This multiplexer, as seen in figure 5, allows the user to select for the output of the logic element either the LUT result directly or the register result. Figure 5: Logic Elements Output Mux
Page 1 and 2: UNIVERSITY OF TORONTO ECE1388 VLSI
Page 3 and 4: There has been a great deal of stud
Page 5 and 6: The final design contains 48 pins.
Page 7 and 8: [1] V. Betz, J. Rose, and A. Marqua
Page 9 and 10: 1. FPGA Design The purpose of this
Page 15 and 16: 4. Routing Routing consists of the
Page 18 and 19: 5. Programming Circuitry We are goi
Page 20 and 21: Caculate SRAMs in logic Block: Logi
Page 22 and 23: Appendix C Cell Circuit Design Repo
Page 24 and 25: Each wire is connected to another t
Page 26 and 27: There are two new components in thi
Page 28 and 29: Pass transistors that connect outpu
Page 30 and 31: Since this connection box only cont
Page 32 and 33: Feedback Buffer: The feedback buffe
Page 34 and 35: The following two circuits are the
Page 36 and 37: NAND:
Page 38 and 39: The following two figures the circu
Page 41 and 42: Schematic Description of program_ro
Page 43 and 44: Figure 2: program_col Schematic Fig
Page 45 and 46: Figure 5: Clock Input to program_ro
Page 47 and 48: Figure 9: Output of Program Figure
Page 53 and 54: Figure 21: Output of Program_data F
Page 55 and 56: Appendix D Full Schematic Design Re
Page 57 and 58: To test the individual tile, and th
Page 59 and 60: To test the tile, we implement the
Page 61:
The first figure shows the programm
Page 64 and 65:
The three by three array of tiles c
Page 66 and 67:
tiles, and then an array of four by
Page 68 and 69:
Appendix E Layout of the Cells Repo
Page 70 and 71:
The SRAM cell is one our base cells
Page 72 and 73:
Switch box interconnects the wiring
Page 74 and 75:
Inverters are standard design, as w
Page 76 and 77:
4-to-1 multiplexer is made out of 3
Page 78 and 79:
Connection Box Bottom Connection bo
Page 80 and 81:
The Input_to_LE cell was designed u
Page 82 and 83:
All the cells passed DRC and LVS. H
Page 84 and 85:
connection_box_right: @(#)$CDS: LVS
Page 86 and 87:
connect_box_bottom: @(#)$CDS: LVS v
Page 88 and 89:
Switchbox: @(#)$CDS: LVS version 4.
Page 90 and 91:
prunenet.out: prunedev.out: audit.o
Page 92 and 93:
Logic Element The Logic Element cel
Page 94 and 95:
Connection Right Block The Connecti
Page 96 and 97:
Switch Block Layout Figure Tile Blo
Page 98 and 99:
Program Row Tile Block The Program
Page 100 and 101:
Program Column Tile Block The Progr
Page 103 and 104:
FPGA Top-Level Schematic:
Page 105 and 106:
The net-lists match. layout schemat
show all

Full-Custom Layout of an SRAM-Based FPGA - University of Toronto

Create successful ePaper yourself

Delete template?

Save as template?