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nc... Freescale Semiconductor, I 118 CHAPTER 8. SEMICONDUCTOR DEVICES Freescale Semiconductor, Inc. Freescale Semiconductor, Inc. to the increase of carriers in the channel due to application of gate voltage. A third type of FET that can operate and in both characteristics are necessary to evaluate their the depletion and the enhancement modes has also comparative been merits from data-sheet specifications. described. The basic differences between these modes can Static mostCharacteristics easily be understood by examining the transfer Static characteristics define the operation of an active characteristics ±±±±±±±±±±±±± of Figure 9. The depletion-mode device device has under the influence of applied dc operating conditions. considerable drain-current flow for zero gate voltage. Drain Of primary interest are those current is reduced by applying a reverse voltage to the gate specifications that indicate the terminal. effect of a control signal on the output current. The V The depletion-type FET GS – is not characterized I with D transfer characteristics curves are illustrated in Figure 9 forward gate voltage. for the three types of FETs. Figure 10 lists the data-sheet The depletion/enhancement mode type device also specifications has normally employed to describe these curves, considerable drain current with zero gate voltage. This as type well as the test circuits that yield the indicated device is defined in the forward region and may have usable specifications. forward characteristics for quite large gate voltages. Notice Figure 5. Channel Enhancement. Application of Of additional interest is the special case of Figure that 8. for Channel the junction Depletion FET, Phenomenon. drain current may be enhanced Positive Gate Voltage Causes Redistribution of Minority tetrode-connected devices in which the two gates are Application by forward of Negative gate voltage Gate Voltage only until Causes the gate-source p-n Carriers in the Substrate and Results the Formation separately accessible for the application of a control signal. Figure 8.18: Principle of operation Redistribution junction of Minority becomes Carriers forward in biased. Diffused Channel of a Conductive Channel Between Source and of MOSFET devices: applying Drain The pertinent a gate voltage redistributes specifications for a junction tetrode are those and Reduces Effective The third Channel type of FET Thickness. operates This only Results in the minority carriers which define drain-current cutoff when one of the gates is in the source-drain mode. Increased This channel. FET Channel has extremely Resistance. Left: low drain enhancement current flow for zero mode An equivalent circuit for the MOSFET is shown in Figure connected to the source MOSFET: and positive the bias voltage is applied to gate-source voltage. Drain current conduction occurs for a 6. Here, voltage C g(ch) is the pulls distributed minority gate-to-channel carriers capacitance ELECTRICAL (electrons) V representing the nitride-oxide capacitance. C gs is the GS CHARACTERISTICS towards the surface, the greater than some threshold value, V GS(th) forming second gate. These a high-conductivity are usually specified as V G1S(off) , . For Gate gate 1 — source cutoff voltage (with Gate 2 connected to voltages greater than the threshold, the transfer gate-source channel, capacitance alsoof called the metal gate inversion area overlapping Because layer. the Centre: basic mode depletion-enhancement of operation for field-effect source), and mode V G2S(off) MOSFET: , Gate 2 — source cutoff voltage (with characteristics are similar to the depletion/enhancement the source, while C gd is the gate-drain capacitance devices of the differs greatly from that of conventional junction Gate 1 connected to source). The negative gate voltage required for mode FET. metal voltage gate area overlapping depletes the drain. conducting C d(sub) and Ctransistors, s(sub) channel, the terminology increasing and specifications the resistance, are drain positive current cutoff voltage with one of the reduces gates connected the to the are junction capacitances from drain to substrate and necessarily source different. An understanding of FET terminology to substrate. resistance Y fs the Right: transadmittance typical between drain I-Vcurrent characteristic for a depletion-enhancement mode MOSFET. Note and gate-source voltage. The modulated channel resistance is rpinch-off ds . R D and R S are atthe high bulk resistances drain-source of the drain and voltage. source. The input resistance of the MOSFET is exceptionally high because the gate behaves as a capacitor with very low leakage (r in 10 14 !). The output impedance is a function of 8.4.2 r ds (which Figure is related 9. Metal-oxide-semiconductor Transfer to the gate voltage) Characteristics and the drain and Associated Scope Traces for the Three FET Types and source bulk resistances (R D and R S field ). effect transistor: MOSFET To turn the MOSFET “on”, the gate-channel capacitance, C g(ch) , and the Miller capacitance, C gd , must be charged. In turning “on”, the drain-substrate capacitance, C d(sub) , must nc... Freescale Semiconductor, I be discharged. The resistance of the substrate For More determinesInformation On This Product, the between peak discharge the current drain for this capacitance. and source Go electrode to: www.freescale.com is controlled by applying electric fields, using The FET just described is called an enhancement-type Figure 6. Equivalent Circuit of Enhancement- a nearby MOSFET. gate A electrode depletion-type MOSFET whichcan isbe electrically made in the insulated from Mode the MOSFET rest of the device. This has the advantage following manner: Starting with the basic structure of Figure 4, a that moderate there resistivity isn-channel no current is diffused between flow from the the gate electrode (in the JFET, there will always be some source and drain so that drain current can flow when the gate small potential current is at zero volts across (Figure 7). In the this manner, depletion the region), giving rise to extremely high input impedances. MOSFET can be made to exhibit depletion characteristics. For There positive gate arevoltages, many the structure ways enhances for achieving in the this aim, one of which is shown in Fig. 8.17. same manner as the device of Figure 4. With negative gate voltage, the enhancement process is reversed and the channel begins to deplete of carriers as seen in Figure 8. MOSFET operation: Although a variety of different MOSFET designs can be distinguished, As with the JFET, drain-current flow depletes the channel area their nearest operation the drain first. relies on the same two fundamental principles (Fig. 8.18). Firstly, by changing The structure of Figure 7, therefore, is both a depletion-mode the gateand voltage, an enhancement-mode depleted device. regions between the source and drain electrodes can be filled with MODES carriers OF OPERATION or, alternatively, conducting channels can be depleted. This allows us to vary the resistance There are two basic of modes the of drain-source operation of FET’s — channel. Secondly, as in the case of the JFET, pinch-off occurs depletion and enhancement. Depletion mode, as previously Figure 7. Depletion Mode MOSFET Structure. mentioned, near refers the to drain the decrease electrode, of carriers in the causing channel the This drain-source Type of Device May Be Designed to Operate in current due to variation in gate voltage. Enhancement mode refers Both the Enhancement to and Depletion saturate. This makes the device Modes 4 MOTOROLA SEMICONDUCTOR APPLICATION INFORMATION Figure 9. Transfer Characteristics and Associated Scope Traces for the Three FET Types MOTOROLA SEMICONDUCTOR APPLICATION For More Information INFORMATIONOn This Product, 3 4 MOTOROLA SEMICONDUCTOR APPLICATION INFORMATION Go to: www.freescale.com For More Information On This Product, Go to: www.freescale.com In a MOSFET, the workhorse of modern electronics, the width of the conducting channel useful as an amplifier. Inversion layer: The above discussion is still somewhat qualitative. It is at the same intuitive level as explaining the operation of a p − n junction diode by discussing the effect of forward or reverse bias on the width of the depletion zone. A more detailed explanation would consider the effect of an external potential on the electronic energy levels of the semiconducting material between source and drain (Fig. 8.19). We see that a bias potential on the gate bends the band edges of the semiconductor beside the insulating barrier. If the bending is large enough, a p-type semiconductor — as shown here — can have the conduction band pulled down below the chemical potential. This creates a narrow channel called an inversion layer, whose width can be modulated by the gate potential eV . The width of the potential well formed at the oxide/semiconductor interface is often narrow
8.5. COMPOUND SEMICONDUCTOR HETEROSTRUCTURES 119 /(0+/-#12 ! ,-. * *&'+ +%+2')!2 3!+%/ !"#$%&'() inversion layer conduction band μ (semiconductor) E c -eφ(z) E v -eφ(z) # " μ (metal) eV valence band (chemical potentials do not have to line up, because insulator blocks current flow.) " Metal Insulator p-type semiconductor Figure 8.19: Band bending induces inversion layer in a MOSFET: applying a positive voltage to the gate electrode causes an electric field across the insulating oxide layer, which penetrates some distance into the semiconductor. This causes a varying potential φ(x) close to the surface of the semiconductor. If the resulting band-bending at the semiconductor/oxide interface becomes larger than the energy gap E g , then the conduction band edge falls below the chemical potential at the surface, causing an inversion layer to form. enough that the levels within it are quantised. New and potentially useful effects arise from the quantisation of energy levels in such quantum well structures (see below). Because the semiconductor in a MOSFET has to be doped in the region were the inversion layer can form, the electronic mean free path, and thereby the mobility, in the quantum well structure is small, which restricts its usefulness. 8.5 Compound semiconductor heterostructures 8.5.1 Bandstructure engineering Another way to make an inversion layer is to change the semiconductor chemistry in a discontinuous fashion within the same crystal structure. Epitaxial, atomic layer-by-layer growth allows the chemical composition and doping to be manipulated in fine detail. Such devices of compound semiconductors are used, for example, in semiconductor lasers for optical discs, in high speed electronics (e.g. cellphones) and high-speed lasers in telecommunications. This technology has also enabled fundamental science, by preparing very high mobility electron systems (e.g. for the quantum Hall effects), making “quantum wires” that are so thin as to have quantised levels, and for studies of the neutral electron-hole plasma as a possible superfluid. Alloys of compound semiconductors, e.g. Al 1−x Ga x As, allow one to continuously vary the optical gap and the position of the band edges by varying the composition x. Two different semiconductors will - when referred to the vacuum potential at infinity - have bands that will
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