Service Manual - AMS Neve

SynchroNet ES/2 Service Manual
CIRCUIT DESCRIPTION
KERNEL Processor, RAM and ROM
The KERNEL microprocessor (U48) is responsible for the following:
User interface.
Machine control.
Controlling ESbus signal routine.
Switching and measuring reference signals.
Controlling the timecode generator.
KERNEL and MACHINE ROMs
The KERNEL’s main ROM - U2 on the program module - is a 27C1001 (or 27C010 depending upon
the manufacturer).
A 27C1001 is a 1Mbit or 128Kbyte ROM but the 6809 can only address a maximum of 64K directly
and so the ROM is arranged into 8 pages of 16Kbytes. The ROM’s address select lines A0 - A13 are
generated by the KERNEL microprocessor while the top 3 address lines are generated by a latch
within the FPGA SPLIT. This latch decodes the ROM’s chip select line (!KERN), the KERNEL’s
data lines (BD0 - BD2) and the R/!W line (!BR/!W) and outputs the lines KA_14, KA_15 and KA_16
which are used to select the current page of the ROM. When the KERNEL’s program wishes to
change page it simply writes the page number to a location in the ROM space.
The ES/2’s MACHINE ROM is also a paged ROM, currently a 27C512 although there is the
capability for fitting 27C1001s in future. The page selection of the MACHINE ROM is similar to the
KERNEL except that the top address line is shared with the KERNEL ROM (KA16).
KERNEL RAM
The KERNEL microprocessor’s RAM (U53 - sheet 1) is a battery backed up 62256 which is a
32Kbyte RAM. The RAM occupies only 16k of address space and so 50% of the RAM is unused.
A MAX791 (U50 - sheet 6) provides supervision of the battery backup. It automatically switched the
RAM’s supply (BVCC) between the main supply and the battery when the +5V supply falls below
4.65V. It also disables the chip select line (!BBRAM) at this point to prevent spurious writes to any
RAM location.
KERNEL EEPROM
To allow the user to select hard reset defaults there is a 512 byte EEPROM on the program module
(U1). The EEPROM used is a National Semiconductors 24C04 (NOTE : some manufacturers have
different pin outs for this chip) which contains an I2C interface. The FPGA SUPPORT generates
the two control lines : a clock signal (EE_C) and a bi-directional data line (EE_D). These signals are
only active when the microprocessor is communicating with the EEPROM.
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