Service Manual - AMS Neve

SynchroNet ES/2 Service Manual
CIRCUIT DESCRIPTION
AK ESbus Interface
The ES/2 communicates with controllers and other ES/2s over 1 of 2 ESbus ports, Bus A or Bus B.
Both busses have the following features :
RS422 serial comms ports.
Timeline bus - to distribute a system wide reference square wave.
TLExt line - open collector line to indicate the presence of a timeline master.
Timecode bus - to distribute a system wide timecode stream.
Frame bus - to distribute a system wide video locked square wave
Drec - a Direct Record Line to eliminate serial delays for consistent punch-ins.
Communicating over the ESbus RS422 port is the exclusive job of the COMMS processor. Figure
18 shows a block diagram of this part of the ES/2. U44 is a 84C42 dual serial control chip which
drives U4A to transmit on ESbus A and U4B to transmit of ESbus B. The RTSA and RTSB lines
from U44 are used to enable the transmitters onto the ESbus. U4D and U4C can transmit onto the
ES/2 receive bus to allow a chase master to send messages to other ES/2s on the bus. Enabling
these transmitters is done via the DTRA and DTRB lines from U44. All transmit enable lines are
active high.
Bus A
{
RS422
i/f
A
Bus B{
RS422
i/f
enable
B
Dual
Serial
i/o
chip
scom_irq
Comms
microprocessor
enable
Figure 18 : COMMS processor ESbus interface
The KERNEL processor is responsible for all of the control signals on the ESbus ports. Figure 19
shows a block diagram of the KERNEL processors’ contribution to the ESbus interface.
The timeline bus is driven by the signal TLRATE generated by CTC3 straight into U5C and U5D for
ESbus A and B respectively. FPGA MCN outputs the bus enable lines busen1 and busen2. U12A
and U12B receive the bus A and B’s timeline respectively, the outputs of which are switched by the
FPGA MCN to provide the ES/2 with its timeline - TLSYNC.
The TLext line is driven by FPGA SUPPORT through an open collector inverter U17B and U17D for
bus A and B respectively. The TLext line is held low if a ES/2 is currently the timeline master i.e. it is
driving the timeline bus. The FPGA SUPPORT is able to read the TLext line of both busses to
determine if there is a timeline master on the bus. If a unit is requested to become a timeline master
when there is already one present then the message “TIMELINE MASTER CONFLICT” will be
displayed and the attempt will be aborted.
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