Service Manual - AMS Neve

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SynchroNet ES/2 Service Manual CIRCUIT DESCRIPTION Timecode interface LTC reader Figure 16 shows a block diagram of the reader. U6D converts the balanced input to a single ended signal while U6A, B, C and U18 is responsible for converting the analogue signal to a TTL level. The processor interface is provided by the Audio Kinetics custom LTC reader gate array (U27). This reads the TTL level LTC, separates and sorts he data and interrupts the KERNEL processor every frame edge or every 1/20th frame rate if no code is present. During winding, if a tach signal is present, the processor will turn off the interrupts from the U27 when the machine goes above 8 x play speed and turns them back on when the machine falls below 5 x play speed. This threshold can be altered with the parameter t_spd, see machine parameter description for further details. The LTC gate array also provides the frame rate signal FSYNC which can be used to lock the generator or timeline signal to MACH reference. The signal !ITCR5F isa5xframe rate signal which is used for servoing. LTC_irq LTCB LTCA Electronically balanced input Analogue to TTL conversion TLTC DAK010 Timecode reader Kernel microprocessor FSYNC iTCR5F TCG Reference Figure 16 : LTC reader Timecode generator The timecode generator can be switched to output 1 of 3 selections : Generated code under processor control. Timecode from the ESbus timecode bus A or B. Reshape the incoming LTC. Figure 17 shows a block diagram of the timecode generator. Issue 1 1:23
CIRCUIT DESCRIPTION SynchroNet ES/2 Service Manual reference tcgref Phase locked loop stability ESBus interface Electronically balanced output TCGA TCGB tcga tcgx2 TCDig B2cod B1cod Kernel microprocessor itcg divider shift register fpga : SPLIT Analogue conditioning LTC reader TLTC clear irq enable fpga:SUPPORT latch latch Level Slew Figure 17 : Timecode Generator The main generator circuitry is situated inside U39 the FPGA SUPPORT. The generator clock is generated by a phase lock loop U30 locked to the TCGREF signal, which is generated by CTC3. This clock, TCGX2 is used to clock data onto a serial line via a shift register. The shift register interrupts the KERNEL processor every 8 bits which loads the next byte into the register, with 1 level of buffering. The processor can alter the path of the generator signal between the shift register and the LTC reader signal TLTC to generate TCDIG. This signal is fed to the ESbus interface to drive the ESbus timecode bus, if selected as master, and also into FPGA SPLIT - U38 - along with the timecode from both ESbus timecode busses. The processor can select which of these 3 signals drive the generator output. The TTL generator signal TCRET is conditioned by U7 and converted to a balanced output by U19. Generator adjustments VR2 is used to adjust the phase locked loop for maximum stability. VR1 adjusts the slew rate of the generator which should be set to 12.5ms for SMPTE or 50ms for EBU code generation. VR6 on the program module adjusts the output level of the generator. 1:24 Issue 1
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Page 3 and 4: Contents SynchroNet ES/2 Service Ma
Page 5 and 6: CIRCUIT DESCRIPTION SynchroNet ES/2
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Page 33 and 34: ES/2 TEST SOFTWARE SynchroNet ES/2
Page 53 and 54: MACHINE PARAMETERS SynchroNet ES/2
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MACHINE PARAMETERS SynchroNet ES/2
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MACHINE PARAMETERS SynchroNet ES/2
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APPENDIX A SynchroNet ES/2 Service
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APPENDIX A SynchroNet ES/2 Service
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APPENDIX B SynchroNet ES/2 Service
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APPENDIX C SynchroNet ES/2 Service
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Index SynchroNet ES/2 Service Manua
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Service Manual - AMS Neve

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