Service Manual - AMS Neve

SynchroNet ES/2 Service Manual
CIRCUIT DESCRIPTION
tach direction and the machine cable resistors. TPOL is used to invert the sense of the tallies so that
the microprocessor always reads high for an active tally.
Tach interface
The ES/2 can read bi-phase or tach and direction across a wide range of speeds. Each time the
ES/2 is calibrated the tach rate is compared with the timecode and a tach divider is set up - unless
disabled by the machine file (top bit of tchdiv set) - to receive a tach rate as close to 1 pulse per
frame as possible. Figure 8 shows a block diagram of the tach circuitry. The circuit diagrams show
the tach analogue conditioning, the tach phase locked loop and the FPGA part of the tach circuit.
TACHB
TACHA
TACH
conditioner
biphase -
tach & dir
convertor
frequency
doubler
fpga : SPLIT
latch
tdir
ITACH
Tally
buffer
Kernel
microprocessor
Programmable
up/down
counter
divider
Reference
stability
fpga : MCN
divider
PL1B
PL1A
Phase
locked
loop
Figure 8 : Tach interface circuit.
There are 3 tach inputs, TACHA, TACHB and TACH COM. The TACH COM line goes to the parallel
machine port to allow each interface to be wired to a potential suitable to the machine. The TACHA
and TACHB signals are buffered by U28 and fed into U26 - a 4583. U26 is a schmitt trigger with
RI4B and RI4C selecting the hysteresis. The output signals TACH1 and TACH2 are fed directly into
FPGA SPLIT.
Inside the FPGA SPLIT there are three sections.
The KERNEL can select the direction signal (TDIR) between the TACH2 signal (tach and
direction) or the output of a bi-phase to tach and direction converter (bi-phase tach).
There is a frequency doubler to increase the low frequency range.
There is a 5 bit divider counter to enable the ES/2 to divide down high frequency tach rates
by up to 32 times.
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