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Service Manual - AMS Neve

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CIRCUIT DESCRIPTION<br />

SynchroNet ES/2 <strong>Service</strong> <strong>Manual</strong><br />

$FFFF -<br />

$C000 -<br />

$8000 -<br />

$4000 -<br />

$0000 -<br />

KERNEL ROM<br />

MACHINE ROM<br />

I/O SPACE<br />

RAM<br />

$7FFF -<br />

ICU1 : U51<br />

$7C00 -<br />

CTC3 : U56<br />

$7800 -<br />

VITC board - expansion<br />

$7400 -<br />

CTC2 : U55<br />

$7000 -<br />

LTC reader chip - U27<br />

$6C00 -<br />

CTC1 : U54<br />

$6800 -<br />

SIO : U44 - ESBUS serial chip<br />

$6400 -<br />

Black hole - expansion<br />

$6000 -<br />

FPGA SPLIT - U38<br />

$5C00 -<br />

DAC - U9<br />

$5B00 -<br />

TALLY latch - U21<br />

$5A00 -<br />

$5900 -<br />

LEDs latch - U31<br />

$5800 -<br />

COMMAND latch - U25<br />

FPGA SUPPORT - U38<br />

$5400 -<br />

FIFO2 : U41 - write to COMMS<br />

$5000 -<br />

FPGA MCN - U36<br />

$4C00 -<br />

FIFO1 : U40 - read from COMMS<br />

$4800 -<br />

INTA : interrupt clear<br />

$4400 -<br />

ICU2 : U52<br />

$4000 -<br />

Figure 5 : KERNEL processor memory map.<br />

Diagnostic port<br />

The ES/2 diagnostic port is a general purpose RS232 serial port which allows the ES/2 to<br />

communicate with a PC. Half of the SIO U49 is used for the diagnostics (the other half for serial<br />

machine control). A 75155 RS232 transceiver is used to convert TTL levels to RS232. The<br />

diagnostic port communicates at 9600 baud with no parity, 8 data bits and 1 stop bit. A list of<br />

commands will be displayed when a ‘’ followed by return is received.<br />

Kernel / Comms interface<br />

The KERNEL and COMMS microprocessors communicate with each other by two uni-directional<br />

First-In-First-Out buffers (FIFOs). The circuit diagrams show 2 MK4501 FIFOs. FIFO1 (U40) routes<br />

messages from the COMMS to the KERNEL while FIFO2 (U41) is concerned with sending<br />

messages from the KERNEL to the COMMS.<br />

There are two hardware status lines generated by each FIFO which inform the processors when<br />

each FIFO is either full or empty. Both processors read these lines via buffers inside the FPGA<br />

SUPPORT. The KERNEL and COMMS processors have the same software to read and transmit to<br />

the FIFOs, a state diagram is shown in Figure 6.<br />

1:10 Issue 1

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