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end structural;File: Avalon_TRX_bus.vhd-- Above: rf_TRX_module.vhd-- RF controler avalon part in VHDL-- The avalon bus is the NIOS altera processor bus. We use a AHB (ARM bus)-- to avalon bus bridge (easier to work with) provided by altera and-- then this module as the interface-- Emanuel . Corthay @ a3. epfl .ch-- Octobre 2003 - EPFL SSC 11entity avalon_TRX_bus is------------------------port ( reset: in std_logic; -- FPGA reset pin-- Avalon bus pinsclk : in std_logic; --chipselect : in std_logic; --read, write : in std_logic; --irq : out std_logic; -- Assert when need to be serviced by a masteraddress : in std_logic_vector(3 downto 0);readdata : out std_logic_vector(31 downto 0);writedata : in std_logic_vector(31 downto 0);-- Module signalsdataW32 : out std_logic_vector(31 downto 0);dataRX32 : in std_logic_vector(31 downto 0);headerTX32 : in std_logic_vector(31 downto 0);headerRX32 : in std_logic_vector(31 downto 0);status32 : in std_logic_vector(31 downto 0);loadTXfifo : out std_logic; -- 1 to loadloadTXfifoReset : out std_logic; -- 1 to load and reset the internal counterrW_TXheaderAvalon : out std_logic; -- 1 to write 0 to read the TX header select with :selectTXheaderAvalon : out std_logic; -- 0 to select header 1 to read or write, 1 for header 2loadCtrlReg : out std_logic; -- 1 to load the control regloadCommand: out std_logic; -- 1 to load the 8 LSB of the control reg (shortcut)selectRXheaderAvalon : out std_logic; -- 1 to readrxFifoReadEn : out std_logic; -- 1 to read in the FIFO RXreadNextRX : out std_logic; -- 1 to read next 32 bits in the fifoRX_reading: out std_logic; -- 1 if a read is in progress in the RX PartTX_writing: out std_logic -- 1 if a write is in progress in the TX Part);end avalon_TRX_bus;architecture synt of avalon_TRX_bus is----------------------------------signal regBufData : std_logic_vector(31 downto 0);signal regBufAddr : std_logic_vector(3 downto 0);type state is (idleS, writeS, readS);signal currentstate, futurestate: state;signal writeExt, readExt: std_logic;begin-- Finite State Machinefsm:process (chipselect, read, write, currentstate)begin-- default outputswriteExt
xFifoReadEn -- ctrlreg32if (writeExt = '1') thenloadCtrlReg -- statusreg3readdata -- TX_fifo normalif (writeExt = '1') thenloadTXfifo
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EPFL - Swiss Federal Institute of T
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The MegaWatch Wireless PlatformMast
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The MegaWatch project : Alim boardW
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MEGAWATCHLSM E.Corthay MFG_DATE: 01
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68591056.3577.2231927.11.03LSM-LAP
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3213434121243214321551K1K1K1KR10R11
Page 94 and 95: EPFL ACORT Mon Dec 1 08:47:30 2003
Page 96 and 97: Component Report MEGAWATCHmegawatch
Page 98 and 99: Single Node Nets Report MEGAWATCHme
Page 100 and 101: Qii8i¡,//4$-r G D/- ’KK•-4K*M.
Page 102 and 103: EPFL ACORT Thu 22.01.2004 11:21 Dra
Page 104 and 105: EPFL ACORT Thu Jan 22 11:21:21 2004
Page 106 and 107: Component Report SABUSALIMsabusalim
Page 108 and 109: BOM Report SABUSALIMsabusalim_gloss
Page 111 and 112: ¬†hx€ƒq‚}ƒr r {o{€ H:
Page 113 and 114: {€}~{ƒ~€z’{r~{{}€rq~h „k
Page 115 and 116: Signal Page Ref ROKEPXA_Brokepxa Th
Page 117 and 118: 10000000000100NC1510KR119U11VALD19B
Page 125 and 126: Component Report ROKEPXA_Brokepexa_
Page 131 and 132: BOM Report ROKEPXA_Brokepexa_gloss
Page 133 and 134: Power Pins Report ROKEPXA_Brokepexa
Page 135 and 136: Extensions Milli-BUS RokEPXAA24 MB_
Page 137 and 138: Extensions Milli-BUS RokEPXAA24 SPI
Page 139 and 140: 24 MHzrf_TRX_moduletxSpeed3 = ctrl3
Page 141 and 142: -- Modify here if you change the st
Page 143: doEmerBut => doEmerBut,inhibitEmer
Page 147 and 148: futurestate txBusyTmp
Page 149 and 150: egPayload
Page 151 and 152: edge)-- If we reached the end of th
Page 153 and 154: -- ################################
Page 155 and 156: RxStbis in std-by)TxStbis in std-by
Page 157 and 158: when idleRx =>rxEn
Page 159 and 160: uf:process (clk, reset)beginif rese
Page 161 and 162: ReadPointer
Page 163 and 164: end process;-- Bufferize the signal
Page 165 and 166: when emerPressed =>bufferedEmerButt
Page 167 and 168: process (clk, reset)beginif (reset=
Page 169 and 170: component sreg8port ( clk : in std_
Page 171 and 172: -- Signals to and from the TXchip_e
Page 173 and 174: component IO_Ctrlport ( clkclkTXres
Page 175 and 176: File: avalon_bus.vhd[…]-- Above:
Page 177 and 178: eginif reset = '1' thencurrentstate
Page 179 and 180: ----------------------------------s
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