Design and Realization of a Prototype Hardware Platform for ...

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The MegaWatch Wireless PlatformMaster's Thesis - Emanuel Corthay6 The MegaWatch Hardware Platform Design6 The MegaWatch Hardware Platform DesignBecause existing hardware did not meet all of our requirements, a new platform has beendesigned. It is described theoretically in this chapter. The associated protocol, software andrealization is explained later in this document.6.1 RequirementsThe main requirements as stated in 4.2 are as follow:Build 20 autonomous, small form factor wireless network units with the following characteristics:- A low-power radio interface to experiment with ad-hoc networks- A second independent radio link for real time monitoring of the units behavior- A powerful, easy to use, flexible processing unit to implement various communicationprotocols and applications- Power management and monitoring capabilities, for the radio subsystems as well as theprocessing unit- An intuitive, simple but yet powerful Human Machine interface to interact with the user- Several extension possibilitiesThe above must be achieved all within 6 months, thus requiring reuse of as much existing or offthe-shelfhardware as possible. Financial constraints also influenced the design choices.6.2 OverviewThe units are separated into 5 main blocks, the 2 independent radio links supported by theMegaWatch extension board, the processor unit and the power supply. The RF link is the lowpowerradio system, whereas WiFi is the Wireless LAN link.UserRFMegaWatch Extension BoardCFWiFiMilli-BUSProcessor UnitA-BUSPower Supply BoardCircuitBoardExternalcomponentBusesFigure 9 MegaWatch Unit System Overview24 / 83
The MegaWatch Wireless PlatformMaster's Thesis - Emanuel Corthay6 The MegaWatch Hardware Platform DesignEach block is linked to the other via a bus. The two bus specifications are the result of team workamong students doing related projects at LAP. They are available on the MegaWatch website at[13] and [14].The Wireless LAN uses a standard Compact Flash (similar to PCMCIA) connector, and the RF isdirectly piggy-backed to the extension board.The processor unit used in this project is a revision of Cédric Gaudin’s original diploma work, theRokEPXA board. The RF and WiFi block are off-the-shelf commercial products that we interfacedthrough the extension board to the system. The MegaWatch board has been entirely designedand built during this project. The power supply board is also an original work, but conducted jointlywith Cédric Gaudin.6.3 Main Processor Board6.3.1 IntroductionThe main board contains the heart of the system. It’s where the various data coming from theperipherals are analyzed and used according to a piece of software that runs on a microprocessor.The software can be stand alone or integrated within an operating system (OS). In the first case, itis compiled for the given processor or microcontroller architecture into fundamental instructionsexecuted sequentially. The developer must take care of everything. Moreover, having twodifferent applications running concurrently is not an easy task.By contrast, it can also be integrated within an OS. For more complex, integrated applications, theOS version is preferred, because a lot of features are made available to the developer throughstandard, portable functions of the operating system.On embedded devices like the MegaWatch units, the available space, computational power andmemory is a scarce resource. Thus, the OS and processor must be carefully chosen toaccommodate these special needs and use the available hardware as efficiently as possible. Atthe same time, the development must be as easy as possible for the developer.Another important thing to consider is the interface, or how to connect a given device to theprocessor. For advanced and wide-spread peripherals like memory, standard system bus definingthe electrical way to connect such a device to a processor exists. Examples include SDRAM, PCI,PCMCIA and CompactFlash. Most commercial processors then implement the bus directly on theprocessor through a certain number of specialized connections (referred to as PINs later in thisdocument), and include the associated controller on the chip. For less demanding peripherals,standard serial controllers for RS-232, I 2 C or SPI buses are usually integrated on most embeddedprocessors. That’s because they are very common for small peripherals like sensors, ADC andmotors, or simply to communicate with a standard PC.This sounds like a very promising interface, but requires fairly complex peripherals with a controllerfor the given bus. At the same time, such a peripheral is usually composed of a monolithic, staticchip known as ASIC (Application-Specific Integrated Circuit). The advantage of these dedicatedchips is their low cost due to high volume manufacturing, and high speed, because the logic on thechip is dedicated to a certain task. On the other hand, if the features offered do not meet therequirements for a system, there is no way to change them. That’s where an intermediate,reprogrammable solution comes into the picture. One such solution is an FPGA, or FieldProgrammable Gate Array. It not only offers a flexible, custom interface solution, but can alsoimplement various programmable functions, as illustrated in figure 10.25 / 83
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The MegaWatch Wireless PlatformMast
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The MegaWatch project : Alim boardW
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MEGAWATCHLSM E.Corthay MFG_DATE: 01
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68591056.3577.2231927.11.03LSM-LAP
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3213434121243214321551K1K1K1KR10R11
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EPFL ACORT Mon Dec 1 08:47:30 2003
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Component Report MEGAWATCHmegawatch
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Single Node Nets Report MEGAWATCHme
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Qii8i¡,//4$-r G D/- ’KK•-4K*M.
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EPFL ACORT Thu 22.01.2004 11:21 Dra
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EPFL ACORT Thu Jan 22 11:21:21 2004
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Component Report SABUSALIMsabusalim
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BOM Report SABUSALIMsabusalim_gloss
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Signal Page Ref ROKEPXA_Brokepxa Th
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10000000000100NC1510KR119U11VALD19B
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Component Report ROKEPXA_Brokepexa_
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BOM Report ROKEPXA_Brokepexa_gloss
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Power Pins Report ROKEPXA_Brokepexa
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Extensions Milli-BUS RokEPXAA24 MB_
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Extensions Milli-BUS RokEPXAA24 SPI
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24 MHzrf_TRX_moduletxSpeed3 = ctrl3
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-- Modify here if you change the st
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doEmerBut => doEmerBut,inhibitEmer
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xFifoReadEn -- ctrlreg32if (writeE
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futurestate txBusyTmp
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egPayload
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edge)-- If we reached the end of th
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-- ################################
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RxStbis in std-by)TxStbis in std-by
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when idleRx =>rxEn
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uf:process (clk, reset)beginif rese
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ReadPointer
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end process;-- Bufferize the signal
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when emerPressed =>bufferedEmerButt
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process (clk, reset)beginif (reset=
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component sreg8port ( clk : in std_
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-- Signals to and from the TXchip_e
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component IO_Ctrlport ( clkclkTXres
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File: avalon_bus.vhd[…]-- Above:
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eginif reset = '1' thencurrentstate
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----------------------------------s
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