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Design and Realization of a Prototype Hardware Platform for ...

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The MegaWatch Wireless <strong>Plat<strong>for</strong>m</strong>Master's Thesis - Emanuel Corthay9 The MegaWatch <strong>Plat<strong>for</strong>m</strong> FabricationThe LCD requires a –5 V generator, implemented on the bottom layer <strong>of</strong> the board. The shutdownPIN <strong>of</strong> this generator is connected to the FPGA, <strong>and</strong> can be used to shut down the LCD to reducepower consumption. The PIN plan <strong>for</strong> the extension board is available in the appendix.Figure 37 Xemics Radio Circuit PINsThe PIN assignments <strong>for</strong> the radio circuit, as shown in figure above is the following:PIN 1PIN 2PIN 3PIN 4PIN 5PIN 6PIN 7PIN 8PIN 9PIN 10PIN 11PIN 12PIN 13PIN 14PIN 15PIN 16PIN 17PIN 18PIN 19PIN 20“SCK”, clock <strong>for</strong> the 3-wire serial busVDD, 3 Volts power supply. Goes through the current sense resistor first.“SI”, input: 3-wire serial bus data signal to the radio circuitGND, ground“SO”, output: 3-wire serial bus data signal from the radio circuit“TX”, set the antenna switch in transmit mode“EN”, 3-wire serial bus enable signal“RX”, set the antenna switch in transmit modeMode0, set the mode <strong>of</strong> the radio circuitNot usedMode1, set the mode <strong>of</strong> the radio circuitPattern signal, goes to 1 when the SFD is detected.Mode2, set the mode <strong>of</strong> the radio circuitNot connected“DCLK”, Recoverd received clockNot connected“Dataout”, output: received dataNot connected“Datain”, input: signal to transmitNot connectedThis signal lines then go to the FPGA through the Milli-Bus, according to the PIN plan given in theappendices.66 / 83

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