Design and Realization of a Prototype Hardware Platform for ...

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The MegaWatch Wireless PlatformMaster's Thesis - Emanuel Corthay6 The MegaWatch Hardware Platform DesignRFCustomPeripheralCustomInterfaceHardwareDataProcessingFPGAStandardBusPeripheralsProcessorMemorySoftwareConfigurationFigure 10 General System PrincipleApplicationSoftwareThe FPGA is basically composed of a large number of logical cells that can implementfundamental logic functions like logical gates, flip-flop and so on. Each cell is configured accordingto a static RAM memory that is loaded at startup from a configuration file sent to the chip. Theresult is a flexible hardware logic system with a software component to configure the embeddedlogic. The FPGA also has drawbacks. It is generally more expensive than an ASIC solution forlarge production, consumes more power (the configuration memory essentially) and runs at lowerfrequency than an ASIC version (fixed wired network). But such a system is very powerful to test adesign (prototyping) before mass production, or for custom, low volume solutions. The reason issimple: you can program a complete system in software that you want your hardware FPGA logicgates to do, and if it does not work as expected, you can simply change the code! The advantageof the software approach (its flexibility) and of the hardware approach (its fast speed for dedicatedtasks) is thus united in a single FPGA circuit.For our application, where flexibility is a requirement, an FPGA solution is ideal. The radiosubsystem can be programmed into this FPGA, changed and tested at will. Also, once a goodradio subsystem runs on the FPGA, a real hardware, gate-level circuit design can be createdautomatically from the FPGA configuration software, and integrated later as part of a dedicatedASIC circuit.6.3.2 Design choiceAltera has a chip family called Excalibur with the nice property of having both an FPGA andcomplete ARM9 processor system in a single chip. It also has the appropriate and integrated toolsto easily combine an FPGA and ARM design into a powerful and versatile system.Moreover, a Linux distribution for the ARM processor architecture exists and is being activelydeveloped as a joint and distributed free software effort around the globe. This last argument setthe operating system that will be used to Linux as the application development environment.The selected Altera Excalibur ARM EPXA1F484C3 [15] chip has the following characteristics:• An ARM922T processor running at 133 MHz• A SDRAM SDR and DDR memory controller (512 Mo max)• Internal 32 Ko SRAM memory• Internal 16 Ko double access SRAM memory• External memory interface of maximum 4 times 32 Mo• Interrupt controller, UART and timers• FPGA with 100’000 logical gates running at 24 MHz26 / 83
The MegaWatch Wireless PlatformMaster's Thesis - Emanuel Corthay6 The MegaWatch Hardware Platform DesignIt is very important to distinguish between the reconfigurable part of the Excalibur, and its VLSIARM part. The reconfigurable part, the FPGA, composed of hardware logic can host manydifferent systems, known as cores, according to a loaded software configuration. Because itcontains both a software and hardware component, it is commonly called “soft-core” where as theVLSI part, burnt for once and for all into the chip, is called “hard-core.” These two componentsinteract with each other through a bridge, present on the chip.Building a Printed Circuit Board (PCB) to link the different hardware circuits for the Excalibur is alot of work. Fortunately, it has been successfully realized in Cédric Gaudin’s Master’s thesis workin March 2003 [16]. The card was named RokEPXA. A slightly modified version, called revision B,of Cédric’s original design was made. The main new feature is the addition of a powermeasurement device explained in 6.6.6.3.3 RokEPXAThe general architecture of the RokEPXA board is as follow:JTAGProgrammingInterfaceRS232PowerMeasurementAlteraExcaliburI 2 CA BUSPowerSupplySDRAMMemory64 MBExtensionConnectorsARMBridgeFPGAI 2 CSerial BusFlashMemory8 MBUSBConnectorFigure 11 RokEPXA rev. B OverviewMilli BUSMegaWatchExtensionThe memory controller of the Excalibur is connected to the two memories. An internal UARTpresent on the ARM part of the Excalibur provides a serial RS-232 interface. The lines dedicatedto the FPGA are connected to various connectors. Around 60 of them are connected to the Milli-Bus, allowing an extension board to be piggy-backed on top of the main board.The programming and debugging interface to the ARM and FPGA are accessible on the boardthough a dedicated connector. The same is true for the microcontroller used for the powermeasurement, as explained in Chapter 6.6.The ARM processor comes with a bus to link it with external peripherals named AHB. The ARMspecifications provide information as to how to communicate on this bus. Two versions of this busare present on the Altera Excalibur chip. The first one, AHB1, is directly connected to the memory27 / 83
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The MegaWatch Wireless PlatformMast
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The MegaWatch project : Alim boardW
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MEGAWATCHLSM E.Corthay MFG_DATE: 01
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68591056.3577.2231927.11.03LSM-LAP
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3213434121243214321551K1K1K1KR10R11
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EPFL ACORT Mon Dec 1 08:47:30 2003
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Component Report MEGAWATCHmegawatch
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Single Node Nets Report MEGAWATCHme
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Qii8i¡,//4$-r G D/- ’KK•-4K*M.
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EPFL ACORT Thu 22.01.2004 11:21 Dra
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EPFL ACORT Thu Jan 22 11:21:21 2004
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Component Report SABUSALIMsabusalim
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BOM Report SABUSALIMsabusalim_gloss
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{€}~{ƒ~€z’{r~{{}€rq~h „k
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Signal Page Ref ROKEPXA_Brokepxa Th
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10000000000100NC1510KR119U11VALD19B
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Component Report ROKEPXA_Brokepexa_
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BOM Report ROKEPXA_Brokepexa_gloss
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Power Pins Report ROKEPXA_Brokepexa
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Extensions Milli-BUS RokEPXAA24 MB_
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Extensions Milli-BUS RokEPXAA24 SPI
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24 MHzrf_TRX_moduletxSpeed3 = ctrl3
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-- Modify here if you change the st
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doEmerBut => doEmerBut,inhibitEmer
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xFifoReadEn -- ctrlreg32if (writeE
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futurestate txBusyTmp
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egPayload
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edge)-- If we reached the end of th
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-- ################################
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RxStbis in std-by)TxStbis in std-by
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when idleRx =>rxEn
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uf:process (clk, reset)beginif rese
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ReadPointer
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end process;-- Bufferize the signal
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when emerPressed =>bufferedEmerButt
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process (clk, reset)beginif (reset=
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component sreg8port ( clk : in std_
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-- Signals to and from the TXchip_e
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component IO_Ctrlport ( clkclkTXres
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File: avalon_bus.vhd[…]-- Above:
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eginif reset = '1' thencurrentstate
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----------------------------------s
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