Design and Realization of a Prototype Hardware Platform for ...

The MegaWatch Wireless PlatformMaster's Thesis - Emanuel Corthay8 The Software* This mechanism is implemented to make sure the receiver is not receiving new data while theprocessor is reading it. The same thing is true for the transmitter.At start-up, this register is initialized so that the transmitter and receiver as well as the buttons areinhibited. It is then important to do an initial write into this register to enable the transceiver!See section 8.2 for more details on the programming interface.8.1.9 CRC Generator and DecoderThe cyclic redundancy code (CRC) is used to detect a transmission error. It works by computing a16 bit checksum of the previous frame bits. This checksum is sent along with the frame andcompared at the receiver with the CRC computed on the receiver side.Polynomial CRCs are widely used for their good mathematical characteristics and easy hardwareimplementation. They generate a 16 bit CRC according to the generator polynomial and appendthem to the transmitted frame. The CRC is calculated based on the header and payload and iscalculated on the fly, no matter what the header and payload size is.In reception mode, the received header and payload is fed into the CRC function, along with the 16bits received CRC. If the result in the CRC register is equal to zero, the received sequence iscorrect.The mathematical concept behind the CRC is outside the scope of this document, but the generalprinciple is simple. Every incoming bit is combined to the previous CRC sequence using XORoperations.More information on CRC can be found in [32].8.1.10 Random Number GeneratorThe random generator is used to provide a pseudo random sequence number when transmitting aping or emergency frame. It is based on a 9 bits Linear Feedback Shift Registers, initialized atstart-up time, and updated at every clock cycle using the previous result. The output is thuspseudo-random, because the output sequence will repeat itself in the same order after a giventime.More information on this pseudo-random number generator can be found in [33]. A more theoryoriented approach is presented in [34].8.2 3-wire Control CoreThis was the first core that was tested, and was used to get familiar with the developmentenvironment, board particularities, and ARM – FPGA interactions. In the same way as with thetransceiver core, the ARM-AHB-Avalon bridge from Altera is used. The various registers can bewritten and read from the ARM. The 3-wire serial bus is described in 7.3.58 / 83