Design and Realization of a Prototype Hardware Platform for ...

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The MegaWatch Wireless PlatformMaster's Thesis - Emanuel Corthay8 The SoftwareRF_bus State machinewait1stop2(si=1)stop1(si=1)clearstart=1busy_out=0write_status=1readD0si=from_dataout_regshift_dataout_reg=1writeD0idleclock_en=0(si=1)en=1readD1readD2writeD1writeD2if start =0if start=1readD3writeD3enablebusy_out=1write_status=1en=0clock_en=0readD4readD5readD6writeD4writeD5writeD6readD7writeD7if rw=1(clock_en=1)writeshift_datain_reg=1init3wiresi=0startdefaults:si=1en=0clock_en=0to_datain_reg=soclearstart=0busy_out=1write_status_reg=0shift_addr_reg=0shift_dataout_Reg=0to_datain_reg=0writeshift_datain_reg=0sendaddr0sendaddr1sendaddr2sendaddr3sendaddr4if rw=0si=from_ctrl_reg[3](read or write)si=from_addr_regshift_addr_reg=1readwriteFigure 34 The 3-wire Finite State MachineIdle:Enable:Init3wire:Start:Readwrite:Sendaddress4 to 0:ReadD7 to D0:WriteD7 to D0:Stop:Wait to start a 3-wire transmissionSend the enable signal on the 3-wire busStart transmitting the clock signal on the busSend the start bitSend 1 to read and 0 to write on the 3-wire bus depending on the read/writebit in the control registerSequentially send the address stored in the address registerRead from the 3-wire into the data in registerWrite to the 3-wire the content of the data out registerSend the stop bits8.3 Other CoresOther cores can be implemented as well on the FPGA, as long as there is enough space on it to fitall of them, and as long as the PINs that each of them access are not the same.60 / 83
The MegaWatch Wireless PlatformMaster's Thesis - Emanuel Corthay8 The SoftwareCore examples include the Compact Flash core, developed by Cédric Gaudin, an interface to linkthe WiFi card to the processor. This work has been under development during this project, and willallow the Linux OS to access the WiFi card.A USB core also exists, developed by a semester student.Also, the I 2 C core is important to use, as it will link the microcontrollers to the FPGA, thus allowingus to access the LCD, keyboard, LEDs and buttons under controller of the microcontroller, as wellas the current measurements. At the moment, the I 2 C is under development by Cédric Gaudin,and it will be finished soon. It is one of the improvements that will take place as explained in 11.3.8.4 Application SoftwareAt this phase of the project, the application software developed on the ARM processor has beenreduced to a minimum. It only comprises the necessary register access to the radio core toinitialize the system.Moreover, the necessary access to the 3-wire core to initialize the Xemics radio circuit are done.In particular, the Starting Frame Delimiter is set to the same sequence programmed in theencoder.The communication between the ARM processor and the microcontroller is not implemented yet. Itis part of the future improvements described in 11.3, and will allow the end user to interact with thesystem through the keyboard and menus to select a receiver unit and send messages.8.5 Microcontroller SoftwareThe software (or rather firmware) running on the microcontroller will be done in a future phase ofthe project (see 11.3). Nonetheless, Cédric Gaudin managed to build a first firmware to validatethe microcontroller functionalities. In particular, it is possible already possible to:• Print characters on the screen• Read and print pressed keys and buttons• Use the LEDs• Print on the on the screen the raw current measurement value• Use the buzzerIn the future, once the I 2 C FPGA core is completed, it will be possible to read and write to themicrocontroller from the ARM processor to build power applications interacting with the user.8.6 ConclusionThe FPGA programming was done in VHDL, a programming language used to describe hardwarefunctions. Because of its physical nature, programming such a system is not trivial. Several clocksrunning at different speeds and unsynchronized are present in the system. To solve that problem,every signal coming from outside of the FPGA has been synchronized to the FPGA clock, bymeans of an intermediate flip-flop register.Also, timing problems arose between some blocks of the radio core. This was caused by thelength of the physical lines in the FPGA that are sometimes too long between blocks. The result isa signal that comes too late with respect to the clock. Adding a flip-flop register on such a line todelay the signal by one clock cycle has been used to tackle those problems.61 / 83
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EPFL - Swiss Federal Institute of T
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The MegaWatch Wireless PlatformMast
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Page 96 and 97: Component Report MEGAWATCHmegawatch
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Page 102 and 103: EPFL ACORT Thu 22.01.2004 11:21 Dra
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Page 106 and 107: Component Report SABUSALIMsabusalim
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Signal Page Ref ROKEPXA_Brokepxa Th
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10000000000100NC1510KR119U11VALD19B
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EPFL ACORT Thu Jan 29 11:01:36 2004
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Component Report ROKEPXA_Brokepexa_
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BOM Report ROKEPXA_Brokepexa_gloss
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Power Pins Report ROKEPXA_Brokepexa
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Extensions Milli-BUS RokEPXAA24 MB_
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Extensions Milli-BUS RokEPXAA24 SPI
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24 MHzrf_TRX_moduletxSpeed3 = ctrl3
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-- Modify here if you change the st
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doEmerBut => doEmerBut,inhibitEmer
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xFifoReadEn -- ctrlreg32if (writeE
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futurestate txBusyTmp
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egPayload
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edge)-- If we reached the end of th
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-- ################################
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RxStbis in std-by)TxStbis in std-by
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when idleRx =>rxEn
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uf:process (clk, reset)beginif rese
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ReadPointer
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end process;-- Bufferize the signal
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when emerPressed =>bufferedEmerButt
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process (clk, reset)beginif (reset=
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component sreg8port ( clk : in std_
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-- Signals to and from the TXchip_e
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component IO_Ctrlport ( clkclkTXres
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File: avalon_bus.vhd[…]-- Above:
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eginif reset = '1' thencurrentstate
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----------------------------------s
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