Design and Realization of a Prototype Hardware Platform for ...

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ProjectThe MegaWatch WirelessPlatformTitleMaster's Thesis - Emanuel CorthayStatusVersion 1.0Keywordsmegawatch, wireless, platform, ad hoc, network,802.11, RF, hardware, transceiver, ARM, linux, watchExecutive SummaryThe MegaWatch project goal was to design and build a wireless network platform composed of 25prototype hardware units to experiment with self-organized, infrastructureless ad-hoc networks.Requirements included reconfigurable, autonomous, low power consumption, and powermeasurement capability. In the long term, it is intended that all the above functionality beintegrated in a small, watch size component.The design chosen was composed of five main blocks: two radio links, a power supply, extensionboard, and processing unit. An off-the-shelf, XE-1202 digital radio circuit from Xemics wasselected as one radio link for low-power, short distance communications. A commercial wirelessLAN card, using the 802.11b standard protocol, provided a second independent monitoring radiolink. The power supply chosen was composed of three voltage regulators, a battery overdischargeprotection, and a power rectifier. The extension board supports both radio systems and contains ascreen, keyboard, buttons and LEDs to interact with the user. Two microcontrollers within theprocessor and extension board contain an ADC converter used for power measurements. The oneon the extension board also controls the LCD and keyboard of each unit. For maximum flexibility,the heart of the system is composed of an Altera Excalibur circuit, made up of an ARM9 systemand a reprogrammable FPGA in a single chip.To run on the ARM9 system, the Linux operating system was selected. It was chosen for the gooddevelopment environment it provides, and the large number of free-software applications anddrivers available for it. The wireless LAN card, connected to the ARM processor, is accessiblefrom Linux to use the available wireless architecture as a monitoring network.A major component of this thesis was the design of a low level CSMA/CA based radio protocol forthe short-range radio link. It was developed for low-data rate operations and implemented into theFPGA in VHDL. Six main functions were implemented including the transmission and reception ofvariable length payload frames of up 64 bytes, 2 FIFO buffers to store the payload, a CRC functionto detect erroneous transmission, as well as a hardware frame generator for ping and emergencymessage transmission. A 3-wire serial interface controller, used to program the external radiocircuit, was also part of the FPGA programming. During the FPGA design phase, importantperformance parameters such as mode switching time and carrier detection system for the radiocircuit were identified.Fabrication of the 25 prototype two layer power supply and extension PCBs was done exclusivelyat EPFL, while the 12 layer main unit PCB was manufactured externally. A total of over 18,000components were ordered.Key future improvements include ad-hoc routing algorithms and application, power measurementsand radio sub system protocol extensions. A Human-Machine-Interface will be developed usingthe keyboard and LCD to build a complete end user ad-hoc application.EPFL – Swiss Federal Institute of TechnologyCopyright © 2004 Emanuel Corthay – emanuel.corthay@a3.epfl.chPermission is granted to copy, distribute and/or modify this document under the terms of the GNUFree Documentation License, Version 1.2 or any later version published by the Free SoftwareFoundation. A copy of the license is included at http://www.gnu.org/licenses/fdl.html
The MegaWatch Wireless PlatformMaster's Thesis - Emanuel Corthay1 IntroductionTable of Contents1 INTRODUCTION 62 SCOPE AND PURPOSE 83 BACKGROUND 103.1 Today’s Wireless Network Systems 103.2 The Next Generation Ad-hoc Network Topology 103.3 Possible Applications 113.4 Existing Standards 114 PROJECT GOALS 144.1 Long Term Vision 144.2 Master’s Thesis Work 165 PRELIMINARY RESEARCH 185.1 DoCoMo’s “Wristomo” Wristwatch mobile phone 185.2 Swatch GSM phone 195.3 Swatch Syncro Beat 195.4 Microsoft SPOT watches 195.5 WiseNET (CSEM) 195.6 BTNodes 205.7 Motes – TinyOS 205.7.1 UC Berkeley Motes (MICA) 205.7.2 Telos 802.15.4 Motes 215.8 IBM Linux Watch 215.9 MICS – Mobile Information and Communication Systems 226 THE MEGAWATCH HARDWARE PLATFORM DESIGN 246.1 Requirements 246.2 Overview 246.3 Main Processor Board 256.3.1 Introduction 256.3.2 Design choice 266.3.3 RokEPXA 276.4 Radio Links 286.4.1 Low Power Ad-hoc Link 286.4.2 WiFi Link 306.5 MegaWatch Extension Board 316.6 Power Measurement 346.7 Power Supply Boards 367 THE PROTOCOLS 383 / 81
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The MegaWatch Wireless PlatformMast
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The MegaWatch project : Alim boardW
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MEGAWATCHLSM E.Corthay MFG_DATE: 01
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68591056.3577.2231927.11.03LSM-LAP
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3213434121243214321551K1K1K1KR10R11
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EPFL ACORT Mon Dec 1 08:47:30 2003
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Component Report MEGAWATCHmegawatch
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Single Node Nets Report MEGAWATCHme
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Qii8i¡,//4$-r G D/- ’KK•-4K*M.
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EPFL ACORT Thu 22.01.2004 11:21 Dra
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EPFL ACORT Thu Jan 22 11:21:21 2004
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Component Report SABUSALIMsabusalim
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BOM Report SABUSALIMsabusalim_gloss
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Signal Page Ref ROKEPXA_Brokepxa Th
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10000000000100NC1510KR119U11VALD19B
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Component Report ROKEPXA_Brokepexa_
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BOM Report ROKEPXA_Brokepexa_gloss
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Power Pins Report ROKEPXA_Brokepexa
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Extensions Milli-BUS RokEPXAA24 MB_
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Extensions Milli-BUS RokEPXAA24 SPI
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24 MHzrf_TRX_moduletxSpeed3 = ctrl3
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-- Modify here if you change the st
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doEmerBut => doEmerBut,inhibitEmer
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xFifoReadEn -- ctrlreg32if (writeE
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futurestate txBusyTmp
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egPayload
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edge)-- If we reached the end of th
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-- ################################
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RxStbis in std-by)TxStbis in std-by
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when idleRx =>rxEn
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uf:process (clk, reset)beginif rese
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ReadPointer
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end process;-- Bufferize the signal
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when emerPressed =>bufferedEmerButt
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process (clk, reset)beginif (reset=
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component sreg8port ( clk : in std_
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-- Signals to and from the TXchip_e
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component IO_Ctrlport ( clkclkTXres
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File: avalon_bus.vhd[…]-- Above:
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eginif reset = '1' thencurrentstate
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----------------------------------s
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