Design and Realization of a Prototype Hardware Platform for ...

The MegaWatch Wireless PlatformMaster's Thesis - Emanuel Corthay6 The MegaWatch Hardware Platform DesignEven though experience is this field exists [17], it would be a Master’s thesis work in itself.Furthermore, the integration of an analog part in a single SoC solution comes later in this long termproject anyways. For all these reasons, it was decided that a commercial off-the-shelf productwould be used for this first prototype in the form of a mounted development kit. This approach alsominimizes the risks and speeds up the prototyping process, in order to have a first working solutionas a proof-of-concept before going further in the project.Several products were considered and compared. Some of their characteristics are shown inTable 1 below. The first priority was to have a small power consumption. That includes theconsumption in transmit mode, but also in receive mode, and most importantly, in idle mode. Theraw transmission power, usually adaptable, is not the main criteria.The link frequency and speed is also of great importance. In general, when the carrier frequencyincreases, the power required to transmit increases as well, but so does the available throughput.For a given low volume traffic, if the speed is too slow, the latency time is greater, and theprobability of having two nodes transmitting at the same time, called a collision, is higher, becauseeach individual transmission lasts longer. On the other end, with a fast transmission, the radiofrequency becomes free much faster after a transmission, reducing the number of requiredretransmissions because of collisions, thus reducing the overall power consumption. Several otherfactors also influence the power consumption of a radio systems, tightly linked to its performance.The best choice is thus not obvious. It is a question of which tradeoff is the best for a givenapplication. More information can be found in [18].Table 1 RF Chip ComparisonIn a previous semester project at LSM, the Nordic circuit was used. But its raw, unsynchronizedoutput makes the usage of a bit synchronizer in hardware outside the chip necessary. By contrast,both the Xemics and Chipcon circuits have a synchronized output and better performance, as wellas extra features like Received Signal Strength Indication (RSSI). The Chipcon chip has a betteroutput power and RSSI selection granularity, some extra power management and encodingfeatures and a faster data rate. The Xemics chip has a built-in pattern recognition system whichsends a signal when a certain synchronization bit sequence is received. The rest of the system isthus discharged of this task, saving power and programming time. It is to be noted that Xemics isa Swiss company, a spin-off of CSEM in Neuchâtel, with which we have good contact. This is ofsignificant importance, and can give the project team a competitive advantage when it comes tointegrating it into a single chip.It is not possible to clearly identify a winner between the Chipcon and the Xemics chip. Eventually,the Xemics development kit XM-1202 [20] available immediately was chosen. Its maincharacteristics are:• Programmable RF output power, max 15 dBm• High reception sensitivity down to –116 dBm• Low power consumption, RX 14 mA, TX 48 mA• Data rate from 4.8 to 76.8 Kbps• On chip frequency synthesizer, bit synchronization and pattern recognition29 / 83